Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-12-20
1999-04-06
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438624, 438659, 438775, 438791, 438694, 438703, H01L 21265
Patent
active
058917985
ABSTRACT:
A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system. When a gate electrode is formed on the dielectric layer, a nitrogen implant into the gate electrode can be used to prevent oxidation at the upper interface of the gate dielectric.
REFERENCES:
patent: 4262056 (1981-04-01), Hubler
patent: 4671845 (1987-06-01), Yoder
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 4948742 (1990-08-01), Nishimura et al.
patent: 5514902 (1996-05-01), Kawasaki et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5629888 (1997-05-01), Saito
patent: 5672251 (1997-09-01), Goto et al.
patent: 5672521 (1997-09-01), Barsan et al.
patent: 5723381 (1998-03-01), Grewal et al.
patent: 5726087 (1994-06-01), Tseng et al.
patent: 5792679 (1993-08-01), Nakato
Kusunoki, S., et al.; "Hot-Carrier-Resistant Structure by Re-Oxidized Nitrided Oxide Sidewall for Highly Reliable and High Prformance LDD Mosfets"; IEEE, 1991; pp. 91-649/91-652.
Doyle, B., et al.; "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing"; IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995; pp. 301-302.
Desu, S. B.; "Influence of Stresses on the Properties of Ferroelectric, BaTiO.sub.3 Thin Films"; J. Electrochem. Soc. vol. 140, No. 10, Oct. 1993; pp. 2981-2987.
Shimizu, S., et al.; "0.15.sup.u m CMOS Process for High Performance and High Reliability"; IEEE 1994; pp. 4.1.1-4.1.4.1.4.
Doyle Brian
Lee Jack
Bowers Charles
Intel Corporation
Nguyen Thanh T.
LandOfFree
Method for forming a High dielectric constant insulator in the f does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a High dielectric constant insulator in the f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a High dielectric constant insulator in the f will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1371183