Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-03-05
2001-02-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S715000, C438S716000, C438S723000, C438S724000, C438S738000, C438S743000, C438S744000
Reexamination Certificate
active
06184147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor fabrication process, and more particularly, to a method for forming a high aspect ratio (HAR) borderless contact hole.
2. Description of Related Art
In order to achieve higher integration of a semiconductor device, a borderless contact process has been implemented in the most current semiconductor fabrication processes. For E-DRAM applications, high aspect ration structure becomes inevitable. Even though the borderless contact process is able to efficiently downsize a semiconductor device to increase the integration, problems, such as how to effectively control the etching process with a properly selected etching end point and etchant, still need to be resolved.
A currently used borderless contact process is schematically illustrated in
FIGS. 1A through 1C
.
Referring to
FIG. 1A
, a silicon nitride layer
14
is formed on a substrate
10
to cover preformed devices including an isolation structure
11
, a gate
12
and source/drain regions
13
of a metal-oxide-semiconductor (MOS) transistor. The silicon nitride layer
14
serves as an etching end point, and provides protection to the isolation structure
11
in the follow-up etching process. A silicon oxide layer
15
is then formed on the silicon nitride layer
14
.
Referring next to
FIG. 1B
, an etching process
17
is performed on the silicon oxide layer
15
to form an opening
16
that exposes a portion of the silicon nitride layer
14
, which is the etching end point. Then, by removing the exposed silicon nitride layer
14
within the opening
16
, a contact hole
16
a
that exposes a portion of the source/drain regions
13
is finished, as shown in FIG.
1
C.
Because the oxide-to-nitride selectivity is the most critical parameter for the foregoing etching process, the profile of the contact hole
16
a
directly relates to the oxide-to-nitride selectivity of the selected etchant. Once an etchant with an improper oxide-to-nitride selectivity is used in the foregoing process, a problem, either over-etching the silicon nitride layer
14
as shown in
FIG. 2A
, or an abnormal termination of the etching process as shown in
FIG. 2B
, further causes electrical malfunction. When an etching process is performed on the silicon oxide layer
15
to form an opening
17
, the etching process is terminated as soon as the silicon nitride
14
is exposed. However, with an improperly selected etchant, a defective opening
17
, as shown in either
FIG. 2A
or
2
B, is obtained. A tapered profile opening
19
as shown in
FIG. 2C
is also a possible defective opening caused by a improperly selected etchant.
As shown in
FIG. 2D
, because polymer molecules generated by the etchant normally tend to deposit on the silicon oxide near the corners of the opening
20
, which further abnormally affects the isotropy of the performed etching process so that a bowed profile opening
20
is obtained. Since in the fabrication process of a highly integrated semiconductor device, a vertical profile, which has lateral walls forming angles of nearly 90 degrees to the surface of the substrate, is required to meet the desired design rule, a bowed profile opening
20
is definitely unable to meet the requirement.
An etching process that uses an etchant with a low oxide-to-nitride selectivity normally leads to either an over-etched as shown in
FIGS. 2A and 2C
. On the other hand, an etchant with a high oxide-to-nitride selectivity tends to cause a bowed profile opening shown in FIG.
2
D and an under etch opening as shown in FIG.
2
B. Therefore, conventionally, a high aspect ration borderless contact process can only concentrate on either one of the options, a vertical profile or a better control of the etching end point, accordingly to the actual needs.
SUMMARY OF THE INVENTION
The method of the invention forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C
4
F
8
/C
2
F
6
/Ar/CO or C
4
F
8
/Ar/CO, on an etcher. The etcher contains a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C
4
F
8
flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C
2
F
6
is about 0.5 to 1.5 times that of C
4
F
8
.
In the mean time, the conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.
The present invention forms a vertical-profile HAR (>4:1) borderless contact hole by using an etchant with a high oxide-to-nitride selectivity without causing over-etching or under-etching.
The present invention provides a method for forming a HAR (>4:1) borderless contact hole to overcome the over-etching and under-etching problems, while also providing a better control of the contact hole profile.
According to the method of the invention the opening with vertical profile of nearly 90 degrees (>89 degrees) can be achieved without sacrificing the oxide to nitride selectivity.
REFERENCES:
patent: 5595627 (1997-01-01), Inazawa et al.
patent: 5817579 (1998-10-01), Ko et al.
patent: 5948701 (1999-09-01), Chooi et al.
Chen Tong-Yu
Huang Keh-Ching
Yang Chan-Lon
Blakely & Sokoloff, Taylor & Zafman
Nguyen Ha Tran
Niebling John F.
United Microelectronics Corp.
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