Method for forming a gate in a semiconductor device

Details Method for forming a gate in a semiconductor device Method for forming a gate in a semiconductor device

2001-11-07

2002-09-17

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

Reexamination Certificate

active

06451639

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method for forming a gate in a semiconductor device, and more particularly, to a method of forming a gate in a semiconductor device using a damascene process.
2. Description of the Related Art
Semiconductor device variables, such as gate width, gate insulating layer thickness, junction depth and the like are progressively being reduced as the integration of a semiconductor is increased. Fabrication methods of polysilicon gates fail to further realize the low resistance required for critical dimensions. In the mean time, developments for a gate having new gate materials as a substitute for polysilicon and having new structures are necessitated. In the past, research and development efforts were focused on a polysilicide gate using transition metal-silicide materials.
However, the polysilicide gate still contains polysilicon as a constituent, which results in increasing the difficulty in realizing low resistance. The polysilicon constituent in the polysilicide gate brings about increasingly effective thicknesses of a gate insulating layer due to a gate depletion effect, as well as threshold voltage variance due to boron penetration/dopant distribution fluctuation in a p+ doped polysilicon gate and the like, thereby limiting the ability to realize low resistance therein.
Boron penetration and gate depletion do not arise in a metal gate using no dopant. Moreover, metal gates use a metal having a work function value corresponding to a mid-band gap of silicon, and when applied to a single gate, thereby enable the formation of a symmetric threshold voltage in NMOS and PMOS areas. In this case, W, WN, Ti, TiN, Mo, Ta, TaN and the like comprise metals of which the work function values correspond to the mid-gap of silicon.
If a semiconductor device is fabricated using a metal gate, difficulty arises in patterning a metal gate, i.e., difficulty of etching, plasma damages in the etching and ion implantation processes and thermal damage caused by a thermal process after the gate formation are generated, thereby reducing the device characteristics.
Accordingly, in order to overcome these perceived disadvantages, a method of forming a metal gate is proposed that comprises the steps of forming a sacrificing gate of polysilicon, forming an insulating layer, removing the sacrificing gate, depositing a metal layer, and polishing the metal layer. The sacrificing gate is replaced by a metal gate, so that a gate is formed without utilizing an etching process. Therefore, the damascene process avoids the problems caused by the etching processes, and also enables use of conventional semiconductor fabrication processes.
FIG. 1A
to
FIG. 1G
illustrate cross-sectional views of a conventional method of fabricating a MOSFET device having a tungsten gate using a damascene process.
FIGS. 2A and 2B
illustrate cross-sectional views illustrating problems resulting from a method of forming a gate in a semiconductor device using a conventional damascene process.
Referring to
FIG. 1A
, a field oxide layer, (not shown in the drawings) defining a device active area, is formed on a surface of a semiconductor substrate
1
and a dummy gate silicon oxide layer
2
is formed on the semiconductor substrate
1
. A dummy gate polysilicon layer
3
and a hard mask layer
4
are then successively formed on the dummy gate silicon oxide layer
2
.
Referring to
FIG. 1B
, a mask pattern
4
a
is formed by patterning the hard mask layer
4
. A dummy gate
5
is then formed by etching the dummy gate polysilicon layer
3
and silicon oxide layer
2
using the mask pattern
4
a.
Referring to
FIG. 1C
, LDD (lightly doped drain) regions are formed in portions of the silicon substrate
1
below both lateral sides of the dummy gate
5
by ion implantation at a relatively low dose and energy. Then, spacers
6
are formed at both sidewalls of the dummy gate
5
by using a known process. Subsequently, source region s and drain region d are formed at the portions of the semiconductor substrate
1
below both lateral sides of the dummy gate
5
by heavy ion implantation.
Referring to
FIG. 1D
, an insulating interlayer
7
is deposited on the semiconductor substrate
1
. The dummy gate polysilicon layer
3
of the dummy gate
5
is exposed by planarizing a surface of the insulating interlayer
7
by using chemical mechanical polishing (hereinafter abbreviated CMP) on the insulating interlayer
7
.
Referring to
FIG. 1E
, the dummy gate, exposed by CMP, is removed. A gate insulating layer
8
is then formed along a surface of the resultant structure. Subsequently, a gate metal layer
9
, such as a tungsten layer, is deposited on the gate insulating layer
8
.
Referring to
FIG. 1F
, a metal gate
9
is formed by polishing the gate metal layer
9
and the gate insulating layer
8
until the insulating interlayer
7
is exposed. Thus, a MOSFET device having the metal gate is completed, as shown.
Unfortunately, the metal gate formed by using the conventional damascene process has disadvantages as described below.
In the process of forming a damascene gate, it is very important to completely remove the dummy gate polysilicon layer
3
and silicon oxide layer
2
. Yet, as shown in
FIG. 2A
, residues of the dummy gate polysilicon layer
3
and silicon oxide layer
2
frequently remain at the corners a of the damascene groove after wet etch, thereby preventing formation of the damascene gate.
Moreover, as shown in
FIG. 2B
, a portion of the silicon oxide layer
2
beneath the spacers
6
may be etched excessively from the bottom corners a of the damascene groove when the dummy gate polysilicon layer
3
and silicon oxide layer
2
are wet-etched. As a result, ‘undercut’ is generated so as to leave voids therein after the gate insulating layer deposition which undercut degrades the gap-filling characteristic when the gate metal is deposited.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of forming a gate in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of forming a gate in a semiconductor device enabling the elimination of the problems resulting at the bottom corners of a damascene groove by carrying out oxidation after dummy gate patterning in a damascene gate forming process.
Additional features and advantages of the present invention will be set forth in the following detailed description, and in part will become apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure described in the written description and particularly pointed out in the claims hereof, as well as being illustrated in the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a method of forming a gate in a semiconductor device includes the steps of forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing successively a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer as a mask pattern and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by carrying out thermal oxidation on the resultant structure after the patterning step, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure after the spacer forming step, polishing the insulating interlayer so as to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers using the insulating interlayer as another etch barrier, depositing a gate insula

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