Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-12
2004-09-07
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S366000, C257S368000, C257S401000
Reexamination Certificate
active
06787854
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing and, more particularly, to forming fins in FinFET devices.
BACKGROUND OF THE INVENTION
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
SUMMARY OF THE INVENTION
Implementations consistent with the principles of the invention form a fin structure in a FinFET device. The fin structure is formed in the shape of a “T” through the use a selective etching process. The T-shaped fin structure allows a greater portion of the gate material to interface with the fin structure thereby improving device performance.
In accordance with the purpose of this invention as embodied and broadly described herein, a semiconductor device includes a substrate, an insulating layer formed on the substrate, a fin structure having a T-shaped cross-section that is formed on a portion of the insulating layer, and a gate formed on the insulating layer and surrounding the T-shaped fin structure.
In another implementation consistent with the present invention, a method for forming a fin structure in a FinFET device is provided. The method includes forming a first dielectric layer on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate, etching the first dielectric layer, and etching the silicon layer to form a T-shaped fin structure, where the etching includes a first etch, a second etch, and a third etch.
In yet another implementation consistent with the principles of the invention, a method for forming a fin structure on a SOI wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate is provided. The method includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.
REFERENCES:
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patent: 6642090 (2003-11-01), Fried et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET; PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Ahmed Shibly S.
Dakshina-Murthy Srikanteswara
Tabery Cyrus E.
Wang Haihong
Yang Chih-Yuh
Advanced Micro Devices , Inc.
Dickey Thomas L
Harrity & Snyder LLP
Tran Minhloan
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