Method for forming a dielectric layer in a semiconductor...

Details Method for forming a dielectric layer in a semiconductor... Method for forming a dielectric layer in a semiconductor...

2001-08-15

2002-05-07

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000, C438S624000, C438S633000, C438S634000

Reexamination Certificate

active

06384482

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention:
The invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method.
2. Description of the Related Art:
In integrated circuits, devices formed in a semiconductor substrate are generally coupled by a system of metallized interconnect. Typically, the manufacturing process is to deposit aluminum or other metal on the semiconductor substrate, and then pattern the deposited metal to form the interconnect.
FIG. 1
shows a typical semiconductor substrate
10
with raised portions such as metal lines
12
formed thereon. A dielectric layer
14
is then formed on the metal lines
12
(first metal lines), as shown in FIG.
2
. In most processes, via holes (not shown) are etched through the dielectric layer
14
, and then second metal lines (not shown) is formed over the dielectric layer
14
. The second metal lines cover the dielectric layer
14
and fill into the via holes to be electrically connected to the first metal lines
12
. The dielectric layer
14
is for insulation between the first metal lines
12
and the second metal lines.
The inter-metal dielectric layer
14
often includes silicon dioxide formed by chemical vapor deposition (CVD). The dielectric layer
14
covers the first metal lines
12
conformably so that the upper surface of the dielectric layer
14
becomes non-planar steps which correspond to the shape of the first metal lines
12
.
The steps in the upper surface of the dielectric layer
14
have several undesirable features. For example, a non-planar surface of the dielectric layer
14
has adverse effects on subsequent photolithographic processes; thereby it deteriorates the optical resolution. In addition, non-planar surface of the dielectric layer
14
interferes with the step coverage of the second metal lines. If the step height is too large, it is possible that the bad step coverage will result in open circuits being formed in the second metal lines.
To solve these problems, one approach is known as chemical mechanical polishing (CMP). The polishing method employs an abrasive chemical to remove protruding steps along the upper surface of the dielectric layer
14
and thus planarizes the steps. The dielectric layer
14
is planarized to form a planarized dielectric layer
14
a
as shown in FIG.
3
.
However, current planarizing methods are still limited. For example, if a manufacturing process requires to polish a dielectric layer, which is above the metal lines, to a remaining thickness of about 1200 to 2500 Å, for instance, it is required that the thickness of dielectric layer between metal lines to be controlled to around 2000 Å in manufacturing a magnetic random access memory (MRAM), the CMP will easily turn to a failure as the metal lines are subject to be polished. This is because the process window of the polishing is small, for example, polishing rate of the silicon dioxide layer is about 3000 Å/min, and thus it is not easy to control the thickness to be polished. Besides, the CMP easily causes defects such as dishing phenomenon.
SUMMARY OF THE INVENTION
An object of the invention is to solve the above-mentioned problems. The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method.
The method for forming a dielectric layer in a semiconductor device in accordance with the invention comprises the steps of: providing a semiconductor substrate having raised portions and recessed portions thereon; forming a first etch stop layer on the raised portions and recessed portions; forming a dielectric layer on the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of the raised portions; forming a second etch stop layer on the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer over the raised portions, and at the same time remaining a plurality of remaining portions of the second etch stop layer on the planarized surface and remaining the dielectric layer between raised portions.
A semiconductor structure having a dielectric layer formed by the method of the invention comprises: a semiconductor substrate having raised portions and recessed portions; a first etch stop layer conformably formed on the raised portions and recessed portions; a plurality of dielectric layers each formed on the first etch stop layer between raised portions, wherein each of the plurality of dielectric layers has a thickness substantially smaller than that of each of the raised portions; and a plurality of remaining portions of a second etch stop layer respectively on each of the dielectric layers, and each of their upper surfaces substantially flush with an upper surface of the first etch stop layer.
In the method of the invention, it is easy to control the extent of the polishing process by using two etch stop layers. That is, since the process window of the method of the invention is larger than that of the prior art, the process can be easily controlled and can lower operation costs and increase production yield.


REFERENCES:
patent: 5560802 (1996-10-01), Chisholm
patent: 6069069 (2000-05-01), Chooi et al.
patent: 6180489 (2001-01-01), Wang et al.
patent: 6218285 (2001-04-01), Lou
patent: 6258711 (2001-07-01), Laursen

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