Method for forming a deep trench capacitor of a DRAM cell

Details Method for forming a deep trench capacitor of a DRAM cell Method for forming a deep trench capacitor of a DRAM cell

1999-05-06

2001-06-05

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C706S032000, C706S032000

Reexamination Certificate

active

06242357

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor device, and more specifically, to a process for manufacturing a deep trench for a Dynamic Random Access Memory (DRAM) cell.
BACKGROUND OF THE INVENTION
With the advance of the integrated circuits technology, the DRAM devices are widely applied in integrated circuits. In generally, A DRAM device comprises many memory cells, and each memory cell typically consists of a storage capacitor and an access transistor for storing each bit by the semiconductor DRAM. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate are connected to external connection lines such as bit lines and word lines, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The digital data is stored in the capacitors and accessed by the MOSFETs, bit lines, and word lines arrays by connecting electrically the capacitors and the sources of the transistors.
However, with the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, for the memory cells in DRAM devices, the most important issue currently is how to promote the storage ability and operation stability of capacitors when the scales of devices still decreases and the integration increases. Thus, the susceptibility of capacitors due to a particle radiation and soft errors is lowered, and the increasing refresh frequency is improved.
For solving the issues above, the prior art approaches to overcome these problems have resulted in the development of the various types of capacitors, such as the trench capacitor and the stacked capacitor. However, The manufacture of the stacked capacitor causes difficulties due to the limitation of the lithography technique. Besides, enormous stacked structures for promoting storage capacity usually cause the crack of the stacked structure occurring due to the unequally stress. On the other hand, the storing capacity of trench capacitor can not be promoted effectively due to the scale of trench capacitor is restricted. In additional, the punch through leakage is also an important issue for manufacturing the trench capacitors with the scale of trench capacitor smaller than micrometer.
SUMMARY OF THE INVENTION
The prime objective of the present invention is to provide a method for manufacturing a deep trench capacitor for a DRAM cell.
The second objective of the present invention is to provide a method for enlarge the surface of the deep trench capacitor of the DRAM cell.
The further objective of the present invention is to enlarge the surface of a capacitor by using a selective etching method.
A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First, an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls adjacent to the bottom. Then, the trench structure is doped to form a doping region on the bottom and a portion of the sidewalls. A selective etching step is performed to remove a portion of the doping region, wherein a selectivity of the doping region is higher than that of undoped sidewalls, and the residual doping region is used to serve as the first storage electrode. Next, a dielectric layer is formed on a top surface of the trench structure. A conducting layer is then formed in the trench structure to be the second storage electrode. A collar oxide layer is formed on the outer surface of the undoped sidewalls. Next, a gate structure is formed on the substrate. A doping step is then used to form the drain/source structures by using the gate structure to be a mask. A strap region is formed to couple electrically the conducting layer and the drain/source structures.


REFERENCES:
patent: 4975383 (1990-12-01), Baglee
patent: 5545583 (1996-08-01), Lam et al.
patent: 5719080 (1998-02-01), Kenney
patent: 5869367 (1999-02-01), Fazan et al.
patent: 5913118 (1999-06-01), Wu
Asahina et al., Etching polysilicon without generating undercut—using chlorine and hydrogen bromide aa processing gases in e.g. microwave plasma etching. English abstract of JP 05243188A, Sep. 1993.

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