Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1998-12-09
2000-11-14
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438396, 438397, 438253, 438255, H01L 2120
Patent
active
061469688
ABSTRACT:
A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed. The method comprises the steps of: forming a first oxide layer onto the substrate; forming a conductive contact plug in the first oxide layer, the contact plug extending down to the substrate; forming a second oxide layer over the first oxide layer and the contact plug; forming a silicon nitride layer over the second oxide layer; patterning and etching the silicon nitride layer and the second oxide layer to form a trench over the contact plug; forming a layer of rugged insitu doped polysilicon layer over the silicon nitride layer and along the walls and bottom of the trench; depositing a photoresist layer over the rugged insitu doped polysilicon layer and filling the trench; performing a first reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is reached; performing a second reactive ion etching step until the rugged insitu doped polysilicon layer lying on the silicon nitride layer is removed, the second reactive ion etching step formulated to remove the rugged insitu doped polysilicon layer faster than the photoresist layer; and performing a chemical dry etching step to smooth out the sharp corners of the rugged polysilicon layer.
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Jeng Shin-Puu
Lou Chine-Gie
Lu Yii-Chian
Davis Jamie L.
Jr. Carl Whitehead
Taiwan Semiconductor Manufacturing Corp.
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