Method for forming a contact hole in a semiconductor device

Details Method for forming a contact hole in a semiconductor device Method for forming a contact hole in a semiconductor device

1994-03-15

1996-02-13

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437189, 437195, B44C 122

Patent

active

054909015

ABSTRACT:
A method for forming a contact hole in a semiconductor device, capable of obtaining a good step coverage in formation of metal wiring and contacts of a highly integrated circuit exhibiting a high topology. The method comprises a primary etching step including the steps of forming a first mask pattern on an insulating film and etching the insulating film by use of the first mask pattern such that a possibly largest area of the insulating film is etched in so far as conduction layers present in the insulating film are not exposed, thereby reducing a topology at an upper portion of the contact region, and a secondary etching step including the steps of removing the first mask pattern, forming a second mask pattern for exposing the contact region, and etching the insulating film remaining over the contact region by use of the second mask, thereby forming a contact hole.

REFERENCES:
patent: 5022958 (1991-06-01), Favreau
patent: 5223084 (1993-06-01), Uesato
patent: 5227013 (1993-07-01), Kumar
Wolf, "Silicon Processing for the VLSI Era" vol. 1-2, Lattice Press, 1990, pp. 529, 534, 539, 551-552-vol. 1, pp. 188-189-vol. 2.

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