Method for forming a carbon doped oxide low-k insulating layer

Details Method for forming a carbon doped oxide low-k insulating layer Method for forming a carbon doped oxide low-k insulating layer

2002-04-25

2004-11-02

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Repair or restoration

C438S475000, C438S779000, C438S784000, C438S798000

Reexamination Certificate

active

06812043

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to semiconductor device manufacturing methods and more particularly to methods for forming a carbon doped oxide low-k insulating layer.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, various layers of insulating material, semi conducting material and conducting material are formed to produce a multi-level semiconductor device. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce capacitance of the insulating layers to allow the insulating layer thicknesses to shrink along with other device features such as metal interconnect line width. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as contact holes when the hole extends through an insulating layer to an active device area, or visa, when the hole extends through an insulating layer between two conductive layers.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization visa and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metallization visa and interconnect lines. For example, in the dual damascene process, a trench opening and via opening is etched in one or more insulating layers also known as an inter-metal or inter-level dielectric (IMD/ILD) layers. The insulating layers are typically formed over a substrate including another conductive area over which the visa and trench lines are formed to provide electrical communication. After a series of photolithographic steps defining via openings and trench openings, via and the trench openings are filled with a metal, preferably copper, to form visa and trench lines, respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, inter-metal dielectric (IMD) layers that make up the bulk of a multi-level device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials with dielectric constants less than about 3.0 technology has become standard practice as semiconductor feature sizes have diminished to 0.13 microns. As feature sizes decrease below 0.13 microns, materials with dielectric constants less than about 2.5 will be required. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0 for achieving device integration in, for example, 0.13 micron interconnections. An exemplary low-k material that is increasingly being proposed for 0.13 micron technology and below, for example, is carbon doped oxide (C-oxide) also known as oregano silicate glass (OSG) formed by a CVD process including where the dielectric constant may be varied over a range depending on the precursors and process conditions. C-oxide, for example, may be formed with dielectric constants over a range of about 2.0 to about 3.0 and density of about 1.3 g/cm
3
compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm
3
for silicon dioxides (e.g., un-doped TEOS).
As might be expected, the development of porous low-k materials has presented several problems in manufacturing methods that must be overcome. Among the problems presented by carbon doped oxide are low strength and proclivity to cracking or peeling in subsequent stress-inducing manufacturing processes including, for example, chemical mechanical planarization (CMP) However, as the dielectric constant decreases, there is a concomitant decrease in hardness. Lower hardness films present serious integration challenges as result of lower adhesion to other films and CMP incompatibility. Above a critical layer thickness of the carbon doped oxide, depending on the hardness of the carbon doped oxide and the induced stresses, the carbon doped oxide becomes susceptible to cracking causing catastrophic failure of the insulating layer. Approaches to protect the low-k insulating material layers, have included the practice to add a capping layer over the insulating layer including for example, silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON) or silicon carbide (SiC). While capping layers have had some success, the addition of the capping layers contributes undesirably to the overall capacitance of the multi-level device. In addition, the capping layers have not been fully effective in preventing crack initiation and propagation through carbon dope oxide layers due to its relatively high brittleness. Other approaches to decrease the cracking susceptibility of the carbon doped oxide layers has been hybrid multiple layered insulating layers composed of, for example, alternating layers of carbon doped oxide and relatively higher dielectric constant layers of, for example, fluorine doped oxide (e.g., FSG).
It would therefore be advantageous to develop a method for forming a carbon doped low-k insulating layer in a multiple layer semiconductor device that has improved hardness and cracking resistance while maintaining or lowering a dielectric constant.
It is therefore an object of the invention to present a method for forming a carbon doped low-k insulating layer in a multiple layer semiconductor device that has improved hardness and cracking resistance while maintaining or lowering a dielectric constant while overcoming other deficiencies and shortcomings of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—R
y
groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.


REFERENCES:
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6114259 (2000-09-01), Sukharev et al.

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