Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-03-25
2004-02-03
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S618000, C438S624000, C438S625000, C438S626000, C438S627000, C438S585000
Reexamination Certificate
active
06686286
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2001-16308, filed on Mar. 28, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method for forming a borderless contact for a semiconductor device and, more particularly, to a method for reducing deterioration of a device due to etching the field oxide in an isolation region when the contact pattern is misaligned by a significant margin during the process for forming the borderless contact holes.
BACKGROUND OF THE INVENTION
It is necessary to reduce the dimensions of both the device elements and the isolation regions between device elements in order to increase the integration density of a semiconductor device. Since the degree of reduction determines size of a cell, a memory cell size is greatly influenced by the device isolation technology.
Conventional methods for manufacturing a field oxide on the isolation region such as “Local Oxidation of Silicon” (“LOCOS”), in which active regions are typically separated by isolation materials grown from the substrate; “Poly-Buffered LOCOS” (“PBL”), in which a stacked structure of an oxide layer, a polycrystalline silicon layer, a nitride layer is formed on silicon substrate; and a trench technique, in which a trench is formed in a silicon substrate and then filled with an insulator are known in the art.
Recently, however, a shallow trench isolation (STI) technique has been used more frequently to form a field oxide in the isolation region.
However, when a borderless contact is formed on a substrate, the insulating material filling the trench, i.e., the field oxide, may be damaged due to a misalignment during the following contact etching step, causing deterioration of semiconductor device characteristics.
A method for forming a borderless contact in a semiconductor device (not shown) is as follows:
First, a field oxide and a gate electrode are sequentially formed on a substrate and an insulation film spacer is then formed on sidewalls of the gate electrode. A silicide layer is then formed on the top of the gate electrodes and in active regions of the semiconductor substrate. A nitride layer, or a stacked structure including a buffer oxide layer
itride layer arrangement, is then deposited on the substrate to protect the field oxide from damage. An interlayer insulation film is then formed on the whole surface and selectively removed to form borderless contacts that exposes a boundary region between the silicide layer and the field oxide on the active region.
When only the nitride layer is used to prevent the field oxide from being damaged, voids in the silicide layer are created by a lattice constant difference between the nitride layer and the silicide layer under the nitride layer. As a result, the semiconductor device characteristics may be degraded by stresses induced in the nitride layer.
On the other hand, when using the buffer oxide
itride layer structure, oxygen penetrates into the active region before formation of the silicide layer, resulting in silicide layer that includes oxygen atoms. As a result, during formation of the buffer oxide layer, the oxygen in the silicide layer out-diffuses and produces a deposited buffer oxide layer about 100 Å thicker than desired due to the reaction of the oxygen with the silane (SiH
4
) used during the deposition process (i.e., an abnormal oxidation). Such an abnormal oxidation damages the field oxide as a result of the difference in thickness between the buffer oxide layer in the active region and the layers on the surface of the field oxide when the stacked layers are removed from the substrate after opening the borderless contact. Moreover, the abnormal oxidation may generate a contact-open failure in the resulting semiconductor device.
As described above, in the conventional method for forming a borderless contact, it is difficult to fill the borderless contact hole as a result of the damage to the field oxide during the borderless contact process etch. It also can create current leakage paths in the field oxide on the isolation region during a connection process with metal lines. As a result, the function and reliability of the semiconductor device will be degraded by the voids in the underlying silicide layer and by the abnormal oxidation that may generate a contact-open fail in the semiconductor device during the borderless contact process.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for forming a borderless contact that minimizes deterioration of the device characteristics by forming a nitride film or a stacked structure of a buffer layer and a nitride film to reduce a damage to the field oxide, and then forming a silicide layer by exposing only the layer on which the silicide layer is deposited.
According to an aspect of the present invention, the method for forming a borderless contact for a semiconductor including a field oxide defining an active region, comprising the steps of: forming a gate electrode on the field oxide of the semiconductor device; forming a stacked structure of a buffer layer pattern and an etching barrier layer pattern on sidewalls of the gate electrode and on the field oxide; forming a silicide layer on the surface of the gate electrode and on the active region which are exposed through the stacked structure; and forming a borderless contact hole.
According to another aspect of the present invention, the method for forming a borderless contact of a semiconductor device, comprising the steps of: forming a field oxide defining an active region on a semiconductor substrate; forming a gate electrode on the field oxide; forming a stacked structure comprising a buffer layer and an etching barrier layer on a whole surface of the semiconductor substrate, including the gate electrode; forming a photoresist pattern which exposes the stacked structure on the gate electrode and on an upper surface of the active region; anisotropically etching the exposed stacked structure using the photoresist pattern as a mask to expose an upper surface of the gate electrode and the upper surface of the active region, and removing the photoresist pattern; forming a silicide layer on the upper surface of the gate electrode and the upper surface of the active region where the stacked structure has been removed; forming a first interlayer insulation film on the whole surface; forming a second interlayer insulation film on the first interlayer insulation film; forming a third interlayer insulation film on the second interlayer insulation film; and forming a borderless contact hole by selectively etching the third, the second, and the first interlevel insulation layers using a contact etch mask to expose a portion of the gate electrode and a portion of the active region.
REFERENCES:
patent: 6207514 (2001-03-01), Furukawa
patent: 6215190 (2001-04-01), Bruce et al.
patent: 6228777 (2001-05-01), Arafa et al.
patent: 6380063 (2002-04-01), Chediak et al.
patent: 2002/0100904 (2002-08-01), Ye et al.
Goudreau George
Hynix / Semiconductor Inc.
Pillsbury & Winthrop LLP
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