Method for forming a 3D interconnect and resulting structures

Details Method for forming a 3D interconnect and resulting structures Method for forming a 3D interconnect and resulting structures

2006-03-21

2008-05-13

Zameke, David A. (Department: 2891)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S455000, C257SE21088

Reexamination Certificate

active

07371662

ABSTRACT:
A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding the first and the second wafers by placing a top surface of the silicon oxide layer against a top surface of the silicon layer and applying a pressure, and forming vias electrically interconnecting integrated circuits in the first and second wafers. The bonding is preferably preformed using a low pressure. A CMP and a plasma treatment are preferably performed to substantially flatten the surface of the silicon oxide layer before bonding.

REFERENCES:
patent: 2004/0152282 (2004-08-01), Tong et al.
Guarini, K. W., et al., “Electrical Integrity of State-of-the-Art 0.13 μm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEDM, IEEE, 2002, pp. 943-945.

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