Method for filling multi-layer chip-stacked gaps

Details Method for filling multi-layer chip-stacked gaps Method for filling multi-layer chip-stacked gaps

2010-03-18

2011-11-01

Everhart, Caridad (Department: 2895)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C257SE21503, C257SE21512, C427S096100, C264S272130

Reexamination Certificate

active

08048721

ABSTRACT:
A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity.

REFERENCES:
patent: 2005/0009259 (2005-01-01), Farnworth
patent: 2007/0178244 (2007-08-01), Torii et al.
patent: 2009/0239336 (2009-09-01), Lee et al.
patent: 2011/0042820 (2011-02-01), Knickerbocker
patent: 2003-064186 (2003-03-01), None
Translation of JP 2003-064186. Mar. 3, 2003, Uchida et al (7 pages).

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