Method for faster timing closure and better quality of...

Details Method for faster timing closure and better quality of... Method for faster timing closure and better quality of...

2006-12-12

2006-12-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07149992

ABSTRACT:
A selective IPO procedure based on the concept of a “timing violation potential” prioritizes the components and nets in a critical path. User input criteria is used to select the components or nets (or both) which have the larger “timing violation potential;” only those components and nets are then operated on. After a selective IPO step, the total number of critical paths is reduced, as well as the worst negative slacks (WNS) of the critical path compared to the traditional IPO method.

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CN 1143860A, Derwent record and abstract, Feb. 26, 1997.

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