Method for fast incremental calculation of an impact of...

Details Method for fast incremental calculation of an impact of... Method for fast incremental calculation of an impact of...

2008-07-08

2008-07-08

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11420529

ABSTRACT:
A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.

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