Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-02-26
2001-06-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06253355
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to very large-scale integrated circuit (VLSI) design and, more particularly, to tools that assist in the design and creation of VLSI circuits.
Current designs of VLSIs include components that number in the millions. Obviously, when dealing with the design of such circuits it is necessary to employ automated tools in order to create, validate and improve the circuit designs and their layouts. Indeed, many tools are available in the art, and different tools cover different aspects of the VLSI circuit creation process, such as
tools that assist in creating the VLSI circuit design,
tools that prepare listings of elements and their connections, in preparations for other automated processes,
tools that analyze the design,
tools the simulate the circuit's operation,
tools that create the circuit layout,
tools that identify the parasitics circuit that corresponds to the circuit's design and layout, etc.
It is important to consider the circuit's parasitic capacitances and resistances because they degrade the circuit's performance and potentially can make the circuit fall outside its intended range of operation. An example of a tool which creates a circuit consisting of the parasitic elements of a given circuit (the “parasitics circuit”) is called “Clover,” which is marketed by the Design Automation Organization of Bell Labs, which is part of Lucent Technologies. Given a circuit design, “Clover” creates the parasitics circuit, expresses it in an established, standardized format, e.g., the “DSPF format , (where DSPF stands for Detailed Standards Parasitic Format), and makes it available for further analysis. Various prior art tools are available that analyze parasitics circuits, such as “SPICE,” which currently is a public domain program.
The problem with current tools for analyzing parasitics circuits is that they are too slow; primarily because they perform all of the necessary calculations, and the number of the required calculations is staggering. The challenge is to quickly evaluate the step response of an analyzed parasitics circuit in order to expedite the overall design process.
SUMMARY
This invention provides a method and a tool for quickly evaluating the impact of parasitics on the functionality of VLSI designs. It quickly identifies, through a simple approximation procedure, the circuit lines where signals are induced by the parasitic capacitances and resistances. When these approximations are in excess of a predetermined threshold, the circuit lines are marked for evaluation with tools that make a more accurate assessment, and if it is determined that these circuit lines do exceed the predetermined thresholds, the circuit designer is alerted to the need to redesign the circuit or its layout.
The tool disclosed herein considers each circuit line of the VLSI circuit, and with respect to each considered circuit line, computes an estimated peak voltage due to the parasitics. The computations are very simple, involving only a summation of terms, each of which involves a quotient of one resistor-capacitor (RC) product by a sum of two RC products. Consequently, the estimate of the peak induced signal on a circuit line is obtained quickly.
REFERENCES:
patent: 5596506 (1997-01-01), Petschauer
A. Rubino, N. Itazaki, X. Xu and K. Kinoshita, “An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 3, p. 387, Mar. 1994.
J. Rubinstein, P. Penfield, Jr., M. A. Horowitz, “Signal Delay in RC Tree Networks”, IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 3, p. 203, Jul. 1983.
T.-M. Lin and C. A. Mead, “Signal Delay in General RC Networks”, IEEE Trans. on Computer-Aided Design, vol. CAD-3, No. 4, p. 331, Oct. 1984.
R. Gupta, B. Tutuianu, and L. T. Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 1, p. 95, Jan. 1997.
D. Martin and N. C. Rumin, “Delay Prediction from Resistance-Capacitance Models of General MOS Circuits”, IEEE Trans. on Computer-Aided Design, vol. 12, No. 7, p. 997, Jul. 1993.
A. Deng and Y-C. Shiau, “Generic Linear RC Delay Modeling for Digital CMOS Circuits”, IEEE Trans. on Computer-Aided Design, vol. 9, No. 4, p. 367, Apr. 1990.
D. S. Gao, A. T. Yang and S. M. Kang, “Modeling and Simulation of Interconnection Delay and Crosstalks in High-Speed Integrated Circuits”, IEEE Trans. on Circuits and Systems, vol. 37, No. 1, p. 1, Jan. 1990.
P. Feldmann and R. W. Freund, “Efficient Linear Circuit Analysis by Pade Approximation via the Lanczos Process”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 5, p. 639, May 1995.
A. Vittal and M. Marek-Sadowska, “Crosstalk Reduction for VLSI”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 3, p. 290, Mar. 1997.
K. L. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design”, IEEE, p. 524, 1996.
S.-Y. Kim, N. Gopal, and L. T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems, vol. 13, No. 10, p. 1257, Oct. 1994.
D. S. Sylvester, C. Hu, O. S. Nakagawa and S.-Y. Oh, “An Analytical Crosstalk Model with Application to ULSI Interconnect Scaling” No Date.
S. D. Corey and A. T. Yang, “Interconnect Characterization Using Time-Domain Reflectometry”, IEEE Trans. on Microwave Theory and Techniques, vol. 43, No. 9, p. 2151, Sep. 1995.
A. J. Rainal, “Transmission Properties of Balanced Interconnections”, IEEE Trans. on Components, Hybrids, and Manufacturing Technology, vol. 16, No. 1, p. 137, Feb. 1993.
Chadha Rakesh H.
Chang Foong-Charn
Ye Lun
Agere Systems Guardian Corp.
Brendzel Henry T.
Do Thuan
Smith Matthew
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