Method for fast ECC memory testing by software including ECC...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07376887

ABSTRACT:
The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

REFERENCES:
patent: 4974184 (1990-11-01), Avra
patent: 6134684 (2000-10-01), Baumgartner et al.
patent: 7062696 (2006-06-01), Barry et al.
patent: 7149947 (2006-12-01), MacLellan et al.
patent: 2005/0044467 (2005-02-01), Leung et al.

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