Method for fast decryption of processor instructions in an...

Electrical computers and digital processing systems: support – Data processing protection using cryptography – Computer instruction/address encryption

Reexamination Certificate

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Details

C713S189000, C711S163000, C711S164000, C726S001000, C726S002000, C726S022000, C726S026000, C726S034000, C712S208000, C712S209000

Reexamination Certificate

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08086871

ABSTRACT:
A method and apparatus for an independent operating system that prevents certain classes of computer attacks. Instruction decryption is performed on an existing instruction set for a processor. The processor architecture limits the impact on processor execution timing. The instruction execution timing is not altered in the processor core and any additional processing is overlapped into existing operations.

REFERENCES:
patent: 2002/0051536 (2002-05-01), Shirakawa et al.
patent: 2002/0101995 (2002-08-01), Hashimoto et al.
patent: 2002/0129244 (2002-09-01), DaCosta
patent: 2002/0194389 (2002-12-01), Worley, Jr. et al.
patent: 2003/0046563 (2003-03-01), Ma et al.
patent: 2004/0117639 (2004-06-01), Mowery
patent: 2004/0240484 (2004-12-01), Argyres et al.
patent: 2004/0255199 (2004-12-01), Yamashita
patent: 2005/0188171 (2005-08-01), McIntosh
patent: 2006/0015748 (2006-01-01), Goto et al.
patent: 2001034474 (2001-02-01), None
patent: 2005018434 (2005-01-01), None
Japan Office Action partial translation Jul. 5, 2011.

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