Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Patent
1999-09-27
2000-11-21
Quach, T. N.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
438131, 438482, 438485, 438600, H01L 2182
Patent
active
061501999
ABSTRACT:
In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
REFERENCES:
patent: 3611063 (1971-10-01), Neale
patent: 3619732 (1971-11-01), Neale
patent: 3629863 (1971-12-01), Neale
patent: 3634927 (1972-01-01), Neale et al.
patent: 3675090 (1972-07-01), Neale et al.
patent: 3677814 (1972-07-01), Gillery
patent: 3699543 (1972-10-01), Neale
patent: 3775174 (1973-11-01), Neale
patent: 3792319 (1974-02-01), Tsang
patent: 4174521 (1979-11-01), Neale
patent: 4199692 (1980-04-01), Neale
patent: 4217374 (1980-08-01), Ovshinsky et al.
patent: 4225946 (1980-09-01), Neale et al.
patent: 4226898 (1980-10-01), Ovshinsky et al.
patent: 4228524 (1980-10-01), Neale et al.
patent: 4312046 (1982-01-01), Taylor
patent: 4424578 (1984-01-01), Miyamoto
patent: 4442507 (1984-04-01), Roesner
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4479088 (1984-10-01), Stopper
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4517223 (1985-05-01), Ovshinsky et al.
patent: 4532702 (1985-08-01), Gigante et al.
patent: 4545111 (1985-10-01), Johnson
patent: 4569121 (1986-02-01), Lim et al.
patent: 4590589 (1986-05-01), Gerzberg
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4677742 (1987-07-01), Johnson
patent: 4726851 (1988-02-01), Matsumura et al.
patent: 4748490 (1988-05-01), Hollingsworth
patent: 4771015 (1988-09-01), Kanai et al.
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4847732 (1989-07-01), Stopper et al.
patent: 4866006 (1989-09-01), Imagawa et al.
patent: 4876668 (1989-10-01), Thakoor et al.
patent: 4882293 (1989-11-01), Naumann et al.
patent: 4914055 (1990-04-01), Gordon et al.
patent: 4933898 (1990-06-01), Gilberg et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5093711 (1992-03-01), Hirakawa
patent: 5181096 (1993-01-01), Forouhi
patent: 5353246 (1994-10-01), Tsang et al.
Adams, A., "Plasma Deposition of Inorganic Films", Solid State Technology, Apr. 1983, pp. 135-139.
Bogdan, A., et al., "An Electrically Programmable Silicon Circuit Board", Mosaic Systems, Inc., pp. 472-476, Date Unknown.
Burns, J. et al., "Applications of Plasma-Deposited SiN to Wafer-Scale Integrated Circuits", IEEE Transactions for Electron Devices, vol. ED-34, No. 11, Nov. 1987, pp. 2374-2375.
Chittick, R., et al., "The Preparation and Properties of Amorphous Silicon", J. Electrochem. Soc., vol. 116, No. 1, Jan. 1969, pp. 77-81.
Cole, B., "ICC Takes the Antifuse One Step Further", Electronics, Mar. 1989, p. 87.
Cole, B., "Programmable Logic Devices: Faster, Denser, and a Lot More of Them", Electronics, Sep. 17, 1987, pp. 61-72.
Cook, B. and Keller, S., "Amorphous Silicon Antifuse Technology for Bipolar PROMS", Bipolar Circuits and Technology Meeting, 1986, pp. 99-100.
El-Ayat, K., et al., "A CMOS Electrically Configurable Gate Array", IEEE International Solid State Circuits Conference, 1988, pp. 76-77.
Gordon, K. and Wong, R., "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse", IEDM, Dec. 1993, pp. 27-30.
Hamdy, E., et al., "Dielectric Based Antifuse for Logic and Memory ICs", IEDM, Dec. 1988, pp. 786-789.
Iversen, W., "Amorphous vias in wafer link chips", Electronics, vol. 56, No. 19, Sep. 22, 1983, pp. 48-49.
Iversen, W., "Amorphous switches add PROM density", Electronics, vol. 57, No. 7, Apr. 5, 1984, p. 54.
Knights, J. and Lujan, R., "Microstructure of plasma-deposited a-Si:H films", Appl. Phys. Lett. vol. 35, No. 3, Aug. 1, 1979, pp. 244-246.
Millman, J. and Halkias, C., Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill Book Company, New York, pp. 58-59.
Morel, D. and Moustakas, T., "Effect of hydrogen on the diode properties of reactively sputtered amorphous silicon Schottky barrier structures", Applied Physics Letters, vol. 39, No. 8, Oct. 15, 1981, pp. 612-614.
Raffel, J., et al., "Laser Programmed Vias for Restructurable VLSI", Massachusetts Institute of Technology, Lincoln Laboratory, International Electron Devices Meeting, Dec. 1980, pp. 132-135.
Raffel, J., et al., "A Demonstration of Very Large Area Integration Usig Restructurable Laser Links", IEEE ISSCC 1982, 9 Pages/Month and Full Magazine Title Not Known).
Raffel, J., et al., "A Demonstration of Very Large Area Integration Using Laser Restructuring", Massachusetts Institute of Technology, Lincoln Laboratory, IEEE International Symposium on Circuits and Systems, vol. 2, May 1983, pp. 781-784.
Raffel, J., et al., "A Wafer-Scale Digital Integrator", Massachusetts Institute of Technology, Lincoln Laboratory, IEEE International Conference on Computer Designs VLSI in Computers, Oct. 1984, pp. 121-126.
Shacham-Diamand, Y., et al., "A Novel Ion-Implanted Amorphous Silicon Programmable Element", IEDM, Dec. 1987, pp. 194-197.
Stopper, H., "A Wafer with Electrically Programmable Interconnections", IEEE International Solid State Circuits Conference, Feb. 1985, pp. 268-269.
Sze, S., Semiconductor Devices: Physics and Technology, 9.2 Dielectric Deposition, John Wiley & Sons, pp. 354-356, 1985.
Vossen, J. and Kern, W., Thin Film Processes, Academic Press, 1978, pp. 526-564.
Wolf, S., et al., "Ion Implantation for VLSI", Silicon Processing, Lattice Press, Inc., 1986, Vol. I, pp. 280-283.
Wyatt, P., et al., "Process Considerations in Restructurable VLSI for Wafer-Scale Integration", Massachusetts Institute of Technology, Lincoln Laboratory, International Electron Devices Meeting, Dec. 1984, pp. 626-629.
"Rad-Hard Vertical Anti-Fuse Technology Reduces IC Geometry", Defense Electronics, vol. 26, No. 5, May 1994, p. 12.
Bechtel Richard L.
Birkner John M.
Chan Andrew K.
Chua Hua-Thye
Thomas Mammen
Quach T. N.
QuickLogic Corporation
LandOfFree
Method for fabrication of programmable interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabrication of programmable interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabrication of programmable interconnect structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1255874