Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-11
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S713000, C438S734000, C216S065000, C216S066000, C216S067000
Reexamination Certificate
active
06380078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of integrated circuit fabrication. More particularly, the invention is in the field of fabrication of damascene interconnects for integrated circuits using copper and low dielectric constant materials.
2. Background Art
The drive to fabricate faster IC (Integrated Circuit) chips is in large part focused on improving the speed of the IC chip interconnect while maintaining or improving other aspects of IC chip performance such as low noise and long term reliability. Interconnect delay is directly proportional to the product of interconnect resistance and the capacitance driven by the interconnect. Thus, in order to improve the speed of the IC chip interconnect, there is need to the reduce the resistivity and the capacitance of the IC chip interconnect. The capacitance of the interconnect is directly proportional to the dielectric constant (“k”) of the dielectric that insulates the interconnect from other interconnect or other circuits of the IC chip. As such, reducing the dielectric constant of the dielectric results in a reduction of the interconnect capacitance and a reduction in the interconnect delay.
Traditionally, aluminum has been used as the primary interconnect conductor and silicon oxide has been used as the primary dielectric in IC chips. Recently, copper has become more desirable as an interconnect conductor at least partly due to the fact that copper has lower resistivity than aluminum. Also recently, a number of low dielectric constant (“low-k”) materials having dielectric constants below that of silicon oxide have been used in IC chips (silicon oxide has a dielectric constant of approximately 4.0). However, the use of copper and low-k dielectric materials has introduced a number of challenges in manufacturing IC chips.
For example, it is difficult to etch copper and as such the “subtractive etch” process used to etch aluminum cannot be successfully used in copper chips. Thus, the present approach to patterning copper interconnect is based on “damascene” processing. The term “damascene” is derived from the ancient in-laid metal artistry originated in Damascus. According to the damascene process, a trench or canal is cut into the dielectric and then filled with metal.
FIGS. 1A through 1D
help describe an overview of the damascene process used to fabricate copper interconnect.
Referring to
FIG. 1A
, insulating layer
102
(for example, silicon oxide) is formed on a substrate
104
, which usually contains circuitry and may contain other interconnection levels. To help with the patterning of copper by the damascene process, layer
102
should have a uniform thickness and be as flat as possible. An ideally flat insulating layer
102
is shown in FIG.
1
A.
FIG. 1B
shows a cross-section of layer
102
after patterning to create two trenches, wide trench
106
and narrow trench
108
. These trenches are formed by removing a top portion of layer
102
using photolithography and a suitable anisotropic etch technique, such as reactive ion etching, which are known in the art. These trenches are where copper interconnect conductors should be laid in. Moreover, the part of layer
102
which is situated between wide trench
106
and narrow trench
108
provides insulation between the copper interconnect to be laid in trench
106
and the copper interconnect to be laid in trench
108
. This part of layer
102
is referred to by numeral
107
. Referring to
FIG. 1C
, copper film
112
is shown as having been deposited over insulating layer
102
. Although not shown in any of the FIGURES, prior to deposition of copper film
112
, a metal barrier layer such as tantalum (Ta) or tantalum nitride (TaN) is deposited over insulating layer
102
. Further, a physical vapor deposition (PVD) copper seed layer (not shown in any of the FIGURES) may also be deposited. Copper film
112
may, for example, be formed by chemical vapor deposition (CVD), PVD, PVD followed by reflow, or electroplating. Preferably, copper film
112
is deposited to a depth such that trenches
106
and
108
are completely filled with copper. Manifestly, the unwanted portions of copper film
112
, for example the portion that is shown as covering part
107
of layer
102
, must be removed.
FIG. 1D
shows a wide inlaid copper conductor
114
and a narrow inlaid copper interconnect
116
remaining in trenches
106
and
108
, respectively, after polishing to remove the unwanted portions of copper film
112
. Polishing is preferably accomplished by chemical-mechanical polishing (“CMP”), wherein the semiconductor wafer and/or a polishing pad are rotatably mounted and brought into contact with each other under rotation. A slurry providing both abrasive and chemically reactive components is supplied, typically to the pad, during polishing. The abrasive component is typically comprised of finely ground colloidal silica or alumina particles. The chemically reactive component is typically diluted acid and/or hydrogen peroxide, with the remainder of the slurry comprised of deionized water. In general, it is desirable that the slurry composition and polishing conditions (e.g. rotational velocity, polish force, temperature) be adjusted such that the conducting films (i.e. the deposited copper film and the metal barrier layer) are selectively removed at a faster rate than the insulating layer (30:1 being a typical ratio) during the CMP.
One drawback of the CMP process, however, is illustrated in FIG.
1
D. The top surface of narrow copper interconnect
116
is shown as slightly “dished” but substantially co-planar with the upper surface of insulating layer
102
. However, wide copper interconnect
114
is shown as severely dished. This effect is referred to as “dishing” in the present application. The dishing phenomenon, such as that shown in wide interconnect
114
, results in an uneven profile in the interconnect layer which, among other things, is harmful to the fabrication process of subsequent layers in the IC chip. In extreme cases, sections of a wide conductor, such as wide conductor
114
, may be completely removed from the trench during polishing, leaving the trench bottom exposed. This total absence of any metal at the central parts of a wide metal conductor is undesirable since, for example, it causes an increase in the resistance of the metal interconnect and also reduces the long term reliability of the IC chip.
In addition to the harmful effects on the fabrication process of subsequent layers in the IC chip, dishing detrimentally affects electrical performance characteristics of the copper interconnects. Copper dishing results in a non-uniform thickness of copper interconnects. As a result of this non-uniform thickness of the copper interconnects the electrical performance characteristics are negatively affected. For example, the resistivity of a copper interconnect is a function of its thickness and as such, the resistivity of a copper interconnect is negatively affected due to non-uniform thickness of the copper interconnect. As another example, the amount of current that a copper interconnect can conduct is dependent on the thickness of the interconnect. A lower thickness results in a more pronounced electromigration problem when high currents are passed through the interconnect. Electromigration results in a loss of metal at certain points in the interconnect which would then result in a reliability problem. Thus, a non-uniform thickness in the copper interconnect may decrease electromigration performance and cause reliability problems.
Another drawback of the CMP process is also illustrated in FIG.
1
D. The sharp edges of insulating layer
102
at the top of the walls in wide trench
106
and narrow trench
108
shown in
FIG. 1C
have been rounded by the CMP process. An example of such rounding effect is pointed to by numeral
115
in FIG.
1
D. This rounding of the sharp edges of insulating layer
102
at the top of the trench walls and subsequent loss of oxide thickness in dense narrow trench arrays (not shown in
Camilletti Lawrence E.
Liu Q. Z.
Berry Renee R.
Conexant Systems Inc.
Farjami & Farjami LLP
Nelms David
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