Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-06-21
2011-06-21
Tran, Tan N (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S067000, C257S069000, C257S353000, C257SE21193
Reexamination Certificate
active
07964916
ABSTRACT:
A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.
REFERENCES:
patent: 4711858 (1987-12-01), Harder et al.
patent: 6020263 (2000-02-01), Shih et al.
patent: 6281102 (2001-08-01), Cao et al.
patent: 6294018 (2001-09-01), Hamm et al.
patent: 6321134 (2001-11-01), Henley et al.
patent: 6353492 (2002-03-01), McClelland et al.
patent: 6759282 (2004-07-01), Campbell et al.
patent: 7052941 (2006-05-01), Lee
patent: 7141853 (2006-11-01), Campbell et al.
patent: 7166520 (2007-01-01), Henley
patent: 7205204 (2007-04-01), Ogawa et al.
patent: 7378702 (2008-05-01), Lee
patent: 7436027 (2008-10-01), Ogawa et al.
patent: 7470142 (2008-12-01), Lee
patent: 7470598 (2008-12-01), Lee
patent: 7508034 (2009-03-01), Takafuji et al.
patent: 7633162 (2009-12-01), Lee
patent: 7671371 (2010-03-01), Lee
patent: 2007/0275520 (2007-11-01), Suzuki
patent: 2008/0038902 (2008-02-01), Lee
patent: 2008/0160726 (2008-07-01), Lim et al.
patent: 2009/0224364 (2009-09-01), Oh et al.
patent: 2009/0325343 (2009-12-01), Lee
patent: 2010/0038743 (2010-02-01), Lee
P. Chen et al., “Effects of Hydrogen Implantation Damage on the Performance of InP/InGaAs/InP p-i-n Photodiodes, Transferred on Silicon,” Applied Physics Letters, vol. 94, No. 1, Jan. 2009, pp. 012101-1 to 012101-3.
D. Lee et al., “Single-Crystalline Silicon Micromirrors Actuated by Self-Aligned Vertical Electrostatic Combdrives with Piston-Motion and Rotation Capability,” Sensors and Actuators A114, 2004, pp. 423-428.
X. Shi et al., “Characterization of Low-Temperature Processed Single-Crystalline Silicon Thin-Film Transistor on Glass,” IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 574-576.
W. Chen et al., “InP Layer Transfer with Masked Implantation,” Electrochemical and Solid-State Letters, Issue 12, No. 4, Apr. 2009, H149-150.
M. Motoyoshi, “3D-IC Integration,” 3rd Stanford and Tohoku University Joint Open Workshop, Dec. 4, 2009, pp. 1-52.
S. Wong et al., “Monolithic 3D Integrated Circuits,” VLSI Technology, Systems and Applications, 2007, International Symposium on VLSI-TSA 2007, pp. 1-4.
J. Feng et al., “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” IEEE Electron Device Letters, vol. 27, No. 11, Nov. 2006, pp. 911-913.
S. Zhang, “Stacked CMOS Technology on SOI Substrate,” IEEE Electron Device Letters, vol. 25, No. 9, Sep. 2004, pp. 661-663.
A.W. Topol et al., “Enabling SOI-Based Assembly Technology for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM Tech. Digest, Dec. 5, 2005, pp. 363-366.
P. Batude et al., “Advances in 3D CMOS Sequential Integration,” 2009 IEEE International Electron Devices Meeting (Baltimore, Maryland), Dec. 7-9, 2009, pp. 14.1.1-14.1.4.
C.S. Tan et al., “Wafer Level 3-D ICs Process Technology,” ISBN-10: 0387765328, Springer, 1st Ed., Sep. 19, 2008, pp. v-xii, 34, 58, and 59.
Beinglass Israel
Cronquist Brian
De Jong Jan L.
Or-Bach Zvi
Sekar Deepak C.
MonolithIC 3D Inc.
Sartori Michael A.
Tran Tan N
Venable LLP
Wang Yao
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