Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-01
2002-06-25
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S660000, C438S663000, C438S664000, C438S683000
Reexamination Certificate
active
06410429
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to a method for forming a void-free epitaxial CoSi
2
layer which is compatible with ultra-shallow source/drain junctions.
2. Description of Prior Art
Self-aligned silicide (salicide) processes are widely used in semiconductor gate and source/drain structures to reduce sheet resistance. As the gate length of transistors are scaled down for each new generation of integrated circuits (IC) in order to achieve higher speeds and higher density, the source/drain junction depths are also scaled down to reduce the short channel effects. Reduced junction depth can significantly increase the sheet resistance for the source/drain regions. For example, for an 800 angstrom junction depth, a salicide process which consumes 300 angstroms of silicon would reduce the junction thickness by more than a third.
Typically salicide processes use titanium silicide. However, as line widths continue to decrease, titanium silicide becomes impractical. This is because titanium silicide sheet resistance increases dramatically as line widths decrease to about 0.17 microns. Cobalt silicide does not exhibit this line width dependance for sheet resistance, making it an attractive alternative to titanium silicide.
Several method for forming a CoSi
2
layer on a shallow source/drain junction have been proposed. In one method, titanium-mediated epitaxy (TIME), a Co/Ti/Si scheme is used. Titanium is deposited onto a silicon structure, preferably by sputtering. Cobalt is deposited onto the titanium, also preferably by sputtering. The substrate is exposed to a two-step anneal in a nitrogen containing ambient, wherein the cobalt and titanium diffuse through one another. The cobalt reacts with the silicon to form CoSi/Co/Si
2
and the titanium migrates to the surface and reacts with the nitrogen to form TiN. This process also removes native oxides through a reaction with the titanium to form TiO. The oxygen is released into the chamber ambient when the titanium reacts with the nitrogen.
Another method for forming CoSi
2
is oxide-mediated epitaxy (OME), which uses a chemical oxide interfacial layer with multiple deposit-and-ultra-high vacuum (UHV) anneal scheme on an initial CoSi
2
layer. However, the UHV in this process increasing fabrication time, reducing throughput. While both methods have demonstrated good epitaxial CoSi
2
on flat (blanket) substrates, voids can occur on patterned substrates in high-stress areas such as adjacent to STI structures.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest, and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,047,367 Wei et al. shows a TIME process wherein the epitaxial CoSi
2
layer is formed by forming a TiN/CoSi bi-layer, using TiN as a diffusion barrier and as a contact via fill. The titanium layer removes native oxide by reacting with the SiO
2
to form titanium oxide (TiO
x
) which travels to the surface and releases the oxygen to the ambient, and titanium silicide (Ti
5
Si
3
and TiSi
2
) remains at the silicon interface. However, Wei does not disclose how the TiN diffusion barrier during annealing will survive the subsequent wet etch step. Also, Wei does not disclose or suggest a void formation issue or a method for preventing void formation in his CoSi
2
scheme.
U.S. Pat. No. 5,194,405 Sumi et al. shows an OME process for the manufacturing of a semiconductor device using a metal silicide film.
U.S. Pat. No. 5,449,642 Tan et al. shows an OME method of forming a metal_disilicide (MSi
2
) film.
U.S. Pat. No. 5,728,625 Tung shows an OME process for device fabrication forming an epitaxal CoSi
2
layer.
U.S. Pat. No. 5,536,684 Dass et al. shows an OME process designed to form a planar epitaxial CoSi
2
layer.
U.S. Pat. No. 5,970,370 Besser et al. shows an unmediated process to form the CoSi
2
layer using a Si/Co/TiN/Ti stack and a 2 step RTA. Detrimental contaminations between the silicon and cobalt are prevented by sputter depositing the cobalt layer and the TiN and Ti capping layers in a vacuum.
U.S. Pat. No. 5,567,652 Nishio shows an OME process to form a CoSi
2
layer using Si/SiO
x
/Ti/Co stack and a 2 step RTA.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a void-free epitaxial CoSi
2
layer on a patterned silicon structure.
It is another object of the present invention to provide a method of fabricating a void-free epitaxial CoSi
2
layer which is compatible with an ultra-shallow junction.
It is another object of the present invention to provide a method of fabricating an ultra-shallow junction by a diffusion process, using a void-free epitaxial CoSi
2
layer as a dopant source.
It is yet another object of the present invention to provide a method of fabricating an ultra-thin (i.e., ≦250 angstroms) CoSi
2
layer suitable for integration into future sub-0.1 micron CMOS architecture.
To achieve these and other objectives, the present invention provides a method for forming a void-free epitaxial cobalt silicide (CoSi
2
) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550° C. and 580° C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrogen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825° C. and 875° C. to convert the CoSi layer to a CoSi
2
layer. The CoSi
2
layer can optionally be implanted with dopant ions which are subsequently diffused to form ultra-shallow junctions.
The present invention provides significant advantages over the prior art. Most significantly, the present invention provides a method for forming a CoSi2 layer which is void free due to reduced stress during annealing, by providing improved control over CoSi/CoSi2 thickness at the silicon interface. Also, the CoSi2 layer formed according to the present invention can be injected with dopant ions and used as a dopant source in a diffusion process to form ultra-shallow junctions with minimal silicon damage.
REFERENCES:
patent: 5047367 (1991-09-01), Wei et al.
patent: 5194405 (1993-03-01), Sumi et al.
patent: 5449642 (1995-09-01), Tam et al.
patent: 5536684 (1996-07-01), Dass et al.
patent: 5567652 (1996-10-01), Nishio
patent: 5728625 (1998-03-01), Tung
patent: 5731239 (1998-03-01), Wong et al.
patent: 5766997 (1998-06-01), Takeuchi
patent: 5924010 (1999-07-01), Chen et al.
patent: 5970370 (1999-10-01), Besser et al.
Chua Soo Jin
Ho Chaw Sing
Karunasiri G.
Lee Kong Hean
Pey Kin Leong
Chartered Semiconductor Manufacturing Inc.
Pham Long
Pike Rosemary L. S.
Saile George O.
Stuffel William J.
LandOfFree
Method for fabricating void-free epitaxial-CoSi2 with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating void-free epitaxial-CoSi2 with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating void-free epitaxial-CoSi2 with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2956395