Method for fabricating thin-film transistor with bottom-gate or

Details Method for fabricating thin-film transistor with bottom-gate or Method for fabricating thin-film transistor with bottom-gate or

1995-10-26

1997-08-19

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438158, H01L 21265, H01L 21465

Patent

active

056588062

ABSTRACT:
A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.

REFERENCES:
patent: 5283455 (1994-02-01), Inoue et al.
patent: 5300446 (1994-04-01), Fujioka
patent: 5395801 (1995-03-01), Doan et al.

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