Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-06-17
2003-11-04
Tran, Thien (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S152000, C438S155000
Reexamination Certificate
active
06642086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Liquid Crystal Display (LCD), and more particularly, to a Thin Film Transistor (TFT) array substrate and a method of fabricating the same.
2. Description of Related Art
Generally, a liquid crystal display (LCD) comprises upper and lower substrates opposing each other with liquid crystal interposed there between, and a thin film transistor (TFT) addressing the voltage to the liquid crystal. On the lower substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in perpendicular direction to the gate lines are formed. In this matrix arrangement, a plurality of TFTs are disposed near the crossover points of the data and gate lines.
Nowadays, the liquid crystal display (LCD) is used for a portable computer such as a laptop computer and is becoming large from the beginning of simple display devices to large size display. The large-sized LCD employs an active matrix array substrate including numerous pixel regions, data and gate lines crossed each other to define the pixel regions, and TFTs (switching device) positioned near the crossover points of the data and gate lines.
In this active matrix type liquid crystal display, a high picture quality and a high definition are current important problems. For this purpose, a method of providing a storage capacitor in parallel with a pixel electrode has been known.
In general, without the storage capacitor, the electric charges of the first signal applied through the TFT for switching the liquid crystal will leak out in a short time after applying the first signal. Therefore, before applying the second signal, the capacitor in parallel with the pixel electrode should be provided to keep up the first electric charges.
In general, for the capacitor the gate line acts as one capacitor electrode and the pixel electrode acts as the other capacitor electrode.
FIG. 1
is a partially enlarged plan view illustrating the array substrate of a conventional active matrix type LCD having a pixel region “P”, a storage capacitor “C”, a TFT “A” and the gate and data lines
35
and
49
. A drain electrode
47
of the TFT “A” is connected to a pixel electrode
40
of the pixel region “P” via a contact hole
57
.
A semiconductor channel region
53
is formed between source and drain electrodes
45
and
47
by exposing the portion of the intrinsic semiconductor layer
39
. Ohmic contact regions are formed between the intrinsic semiconductor layer
39
and the source and drain electrodes
45
and
47
. And gate and data pads (not shown) are formed at one end of the gate and data lines
35
and
49
.
FIGS. 2
a
to
2
f
cross-sectional views taken along line I—I of
FIG. 1
, illustrating process steps of fabricating a TFT array substrate using a conventional four-mask process.
Referring to
FIG. 2
a
, a first metallic layer (not shown) is formed on a substrate
31
and is patterned using a first mask process to form the gate pad (not shown), gate electrode
33
and gate line
36
. The first metallic layer is made of a metallic material having a low resistance, such as Aluminum (Al) or Al-alloy. When the gate line is used for the capacitor electrode, the time constant of the gate line increases. Thus, the material having the low resistance such as Aluminum is preferably used for the gate line. This means that Aluminum can decrease the time constant compared with the material having a high resistance such as Tantalum (Ta) or Chrome (Cr).
The gate electrode
33
extended from the gate line
36
is formed at the corner of the pixel region. Referring back to
FIG. 1
, a portion of the gate line
36
is used for a capacitor electrode of the storage capacitor “C”.
As shown in
FIG. 2
b
, a first insulation layer
37
is formed by depositing an inorganic substance such as Silicon Nitride (SiN
x
) and Silicon Oxide (SiO
2
) or an organic substance such as BCB (Benzocyclobutene) and acryl on the substrate
31
while covering the gate electrode
33
and the gate line or capacitor electrode
36
. Then intrinsic semiconductor layer
39
, such as pure amorphous silicon, is formed on the first insulation layer
37
. Then extrinsic semiconductor layer
41
, such as impurity (n+ or p+) doped amorphous silicon, is sequentially formed on the intrinsic semiconductor layer
39
. Then a second metallic layer
43
made of a material such as Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Antimony (Sb) and the like is formed on the extrinsic semiconductor layer
41
.
Referring to
FIG. 2
c
, the source and drain electrodes
45
and
47
, data line
49
(see FIG.
1
), data pad (not shown) and second capacitor electrode
51
having an island shape are formed by patterning the second metallic layer
43
and extrinsic semiconductor layer
41
using a second mask process. The source and drain electrodes
45
and
47
are spaced apart from each other to expose the semiconductor channel region
53
. At this time, the extrinsic semiconductor layer
41
is removed using the source and drain electrodes
45
and
47
as a mask. Moreover, carefulness is needed, in this etching step, not to pattern the intrinsic semiconductor layer
39
.
The portions of the extrinsic semiconductor layer
41
, between the intrinsic semiconductor layer
39
and the source and drain electrodes
45
and
47
, act as ohmic contact layers
43
a
and
43
b
, respectively.
As shown in
FIG. 2
d
, a second insulation layer or protection layer
53
is formed on the metallic layers
45
,
47
and
51
and intrinsic semiconductor layer
39
.
Referring to
FIG. 2
e
, the contact holes
55
and
57
are formed by patterning the protection layer
53
. Simultaneously, the pixel region “P” are formed by patterning the protection layer
53
, intrinsic semiconductor layer
39
and first insulation layer
37
using a third mask process except the region for the storage capacitor and the data line.
Referring to
FIG. 2
f
, a transparent conductive substance such as ITO (indium-tin-oxide) is deposited and patterned using a fourth mask process. Thus, the pixel electrode
40
, electrically connecting to the second capacitor electrode
51
and drain electrode
47
via contact holes
51
and
57
, is formed.
FIG. 3
a
is an enlarged view illustrating the portion “C” of
FIG. 2
f
and
FIG. 3
b
is an equivalent circuit view of
FIG. 3
a.
As shown in
FIGS. 3
a
and
3
b
, the storage capacitor “C” includes the first capacitor electrode or the gate line
36
. It also includes the second capacitor electrode
51
(having a contact with the pixel electrode
40
), first insulation layer
37
(which stores the electric charge as a dielectric layer) and semiconductor layer
42
(the intrinsic and extrinsic semiconductor layers
39
and
41
as a dielectric layer).
According to the conventional method for manufacturing the TFT array substrate using the four-mask process, the process steps are decreased. However, the storage capacitance is also decreased compared to that of the array substrate manufactured using the five-mask process. For better description, the storage capacitance is represented by the following equation:
C
st
=
ϵ
·
A
d
(
1
)
In the above equation (1), where “C
st
” denotes capacity, “&egr;” denotes a dielectric constant, “d” represents the thickness of the dielectric layer and “A” represents the area of the capacitor electrode. As described in the Equation (1), the storage capacitance “C
st
” is in proportion to the amount of the area “A” and is in inverse proportion to the thickness “d” of the dielectric layer.
Therefore, due to the fact that the dielectric layer includes two layers (the first insulation layer
37
and semiconductor layer
42
) between the two capacitor electrodes
36
and
51
, in the conventional four-mask process, the capacitance is decreased.
SUMMARY OF THE INVENTION
In order to overcome the problems described above, a preferred embodiment of the present invention provides a method of fabricating a TFT array substrate having a large storage capa
Kim Yung-Wan
Lim Byoung-Ho
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Tran Thien
LandOfFree
Method for fabricating thin film transistor array substrate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating thin film transistor array substrate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating thin film transistor array substrate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3120790