Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-05-13
2001-10-09
Tran, Andrew (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S166000
Reexamination Certificate
active
06300175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a method for fabricating Thin Film Transistor (TFT), and more particularly, to a method for fabricating TFT, of which an active layer is formed by crystallizing a silicon thin film, using Sequential Lateral Solidification (SLS).
2. Description of Related Art
In order to fabricate TFTs on a low heat-resistant substrate, such as a glass substrate, an amorphous silicon layer or a polycrystalline silicon layer is deposited on the substrate and is etched by photolithography to form active layers for TFTs.
The mobility of a carrier is low in the amorphous silicon layer. Accordingly, amorphous silicon TFT is difficult to be used as a device for driving circuits of a liquid crystal display (LCD). However, the mobility of a carrier is high in the polycrystalline layer. Accordingly, polycrystalline TFT could be used as a device for driving circuits of a liquid crystal display (LCD), in which devices for pixel array and a device for driving circuits are formed simultaneously.
There are two techniques to form polycrystalline silicon film on a glass substrate. In the first technique, an amorphous silicon film is deposited on the substrate and is crystallized under a temperature of 600 C by Solid Phase Crystallization (SPC). The first technique needs a high temperature process. Therefore, it is difficult to form the polycrystalline silicon film layer on the glass substrate by the first technique.
In the second technique, an amorphous silicon film is deposited on the substrate and is crystallized by thermal treatment using a laser. The second technique does not require a high temperature process. Therefore, the second technique is applied to form a polycrystalline silicon film on the glass substrate.
FIG. 1A
to
FIG. 1E
are schematic drawings for explaining a method for fabricating a TFT according to the prior art.
Referring to
FIG. 1A
, a source electrode
11
S and a drain electrode
11
D are formed on an insulating substrate
100
. And an amorphous silicon layer
12
is deposited on the exposed surface of the substrate comprising the source electrode
11
S and the drain electrode
11
D. The amorphous silicon layer
12
has steps and sloping surfaces, since the amorphous silicon layer
12
covers the protruding source and drain electrodes
11
S and
11
D.
Referring to
FIG. 1B
, the amorphous silicon layer is crystallized into a polycrystalline silicon layer
13
by carrying out a crystallization procedure using laser annealing. The method for crystallizing the amorphous silicon layer into the polycrystalline silicon layer
13
by applying a laser beam to the amorphous silicon layer is described as follows.
An active layer of the TFT is formed by the polycrystalline silicon layer having large silicon grains to decrease the effect of the grain boundary which prevents carriers from passing through the channel.
A selected region of the amorphous silicon layer is first irradiated with an energy density to induce separated islands of amorphous silicon, remaining. The other regions undergo complete melting. The amorphous film is translated or moved relative to the laser beam over a distance less than a predetermined distance for a second irradiation. While the film is translating, the separated islands of amorphous silicon are used as seeds and grow into the molten silicon region, to form a first polycrystalline silicon region. Herein, grain growth occurs from the interface between the liquid silicon region and the solid state amorphous silicon region into the liquid silicon region. This grain growth stops by making grain boundary when each grain collides. The above-described process of irradiating and crystallizing is repeated over a total translation distance to crystallize the majority of the film.
Referring to
FIG. 1C
, the polycrystalline silicon layer is etched by photolithography to form an active layer
14
. Referring to
FIG. 1D
, a gate insulating interlayer
15
and a gate electrode
16
are formed on the active layer
14
. Source and drain regions
14
S and
14
D are then formed in the active layer
14
by doping impurities in the exposed portions of the active layer
14
. The channel region
14
C is formed between the source and the drain regions
14
S and
14
D.
Referring to
FIG. 1E
, a passivation layer
17
is deposited on the exposed surface of the substrate and is etched selectively to expose a portion of the drain electrode
11
D. And a pixel electrode
18
is formed connecting the exposed portion of the drain electrode
14
D on the passivation layer
17
.
However, since the size of each silicon grain is non-uniform and the location of grain boundary is random in the active layer, device-to-device uniformity is low in TFTs fabricated according to the prior art. Therefore, the polycrystalline silicon layer connot be applied to form devices having complicated circuits, while a single crystal silicon film could be applied to form such device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for crystallizing an amorphous silicon layer and a method for fabricating a TFT, that substantially obviates one or more of the problems due to limitations and disadvantages of the prior art.
Another object of the present invention is to provide a method for fabricating a TFT, the active layer of which is formed by crystallizing a silicon thin film, using steps by Sequential Lateral Solidification (SLS).
A further object of the present invention is to provide a method for fabricating a TFT, the active layer of which is formed by using a large single silicon grain.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention, a method for fabricating a TFT having an active layer formed by crystallizing an amorphous silicon layer, comprises forming the active layer having sloping and flat surfaces by selective etching of the crystallized silicon layer; crystallizing the amorphous silicon layer by SLS technique, using a laser beam having energy density so as to melt the sloping surface as well as the flat surface of the amorphous silicon layer.
In another aspect of the present invention, a method for fabricating a TFT comprises steps of: forming source and drain electrodes on a substrate; depositing an amorphous silicon layer on the exposed portion of the substrate comprising the source and the drain electrodes; crystallizing the amorphous silicon layer by SLS technique; forming an active layer by etching the crystallized silicon layer through photolithography; forming a gate electrode and a gate insulating layer on the active layer; and forming source and drain regions in the active layer by doping impurities selectively in the exposed portion of the active layer.
In another aspect of the present invention, a method for fabricating a TFT, comprising steps of: forming a gate electrode on a substrate; forming a gate insulating layer on the exposed portion of the substrate comprising the gate electrode; depositing an amorphous silicon layer on the exposed portion of the gate insulating layer; crystallizing the amorphous silicon layer by SLS technique; forming an active layer by etching the crystallized silicon layer through photolithography; and forming source and drain electrodes connecting the active layer electrically.
REFERENCES:
patent: 5432122 (1995-07-01), Chae
patent: 5496768 (1996-03-01), Kudo
patent: 5585647 (1996-12-01), Nakajima et al.
patent: 5696388 (1997-12-01), Funada et al.
patent: 5767003 (1998-06-01), Noguchi
patent: 5817548 (1998-10-01), Naguchi et al.
paten
LG. Philips LCD. Co., Ltd.
Long Aldridge & Norman LLP
Tran Andrew
Wilson Christian D.
LandOfFree
Method for fabricating thin film transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating thin film transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating thin film transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2585065