Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-08-10
2002-09-10
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S587000, C438S182000
Reexamination Certificate
active
06448163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a T-shaped gate structure and method for fabrication of transistors which include T-shaped gates.
2. Description of the Related Art
Increasing the density of devices formed in integrated circuits involves a corresponding reduction in the size or scale of the devices. With a reduction in feature size of transistors in integrated circuits, a corresponding reduction in a transistor's gate dimensions gives rise to a number of performance issues for traditional devices. Reducing the conventional gate structure of a transistor can give rise to an increase in parasitic capacitance and a difficulty in contacting the very small gate structures necessary in small-scale devices. These limitations can become a performance limiting factor. To overcome these limitations, T-shaped gates have been proposed. The T-shaped gate is so named because the cross-section of the conductive gate material has a T-shaped appearance, with a base section (closer to the surface of a substrate) having a narrower width than contact section (at the top of the gate, where conductive interconnects engage the gate).
Along with multiple types of T-shaped gate structures, a number of methods have been proposed to form such T-shaped gates. One such method is disclosed in U.S. Pat. No. 5,998,285. The method taught therein seeks to eliminate the use of the traditional reactive ion etching processes to define the gate structure. In particular, a silicon nitride layer and a pad oxide are formed on a silicon substrate after which a BPSG layer is formed and etched back to expose the silicon nitride surface. The silicon nitride is then removed and a first poly layer is provided and planarized. Thereafter, a second polysilicon layer is formed by selective CVD on the first poly layer to achieve a T-shaped gate electrode. This avoids the directional etch (typically RIE) conventionally used to remove portions of the first poly layer to form the gate structure. A second implant is used to provide self-aligned source and drain areas for the transistors.
The aforementioned process, however, and prior art techniques provide no truly effective mechanism for defining all dimensions of the gate cross-section and therefore producing the desired configuration of the device.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a T-shaped gate and a transistor utilizing such gate with the gate having well defined dimensions.
In one aspect, the invention, roughly described, comprises a method of forming a T-shaped gate for a transistor, comprising: defining a base length of the gate by forming a gate stack on a substrate; defining a contact length by forming a layer of nitride on the gate stack; and defining gate height by selectively removing portions of the nitride layer.
In a further aspect, the method includes the further step of defining a contact height by depositing a conductive layer on said gate stack.
In a further aspect, the base length is defined by forming a gate oxide on the surface of the substrate; depositing a layer of polysilicon on the surface of the gate oxide; and selectively etching portions of the polysilicon layer to define said base length.
In still another aspect, the contact length is defined by depositing a protective oxide on the surface of the gate stack having a thickness; and depositing said layer of nitride having a thickness which, when added to the thickness of the oxide layer and doubled, and added to the base length, will equal the contact length of the gate stack.
In yet another aspect, the gate height is defined by depositing a thick oxide on the surface of the nitride layer; polishing the oxide down to the surface of the nitride layer; etching said nitride layer; and depositing a second conductive layer on said gate stack.
In another aspect of the invention, two polysilicon layers are used, one to form the contact length portion of the gate and the other to form the base length portion. In one embodiment, a silicide layer is provided between the layers.
REFERENCES:
patent: 4839304 (1989-06-01), Morikawa
patent: 6239007 (2001-05-01), Wu
Cherian Sunny
Holbrook Allison
Krivokapic Zoran
Advanced Micro Devices , Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Pham Long
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