Method for fabricating stacked chip package

Details Method for fabricating stacked chip package Method for fabricating stacked chip package

2001-01-05

2003-01-07

Jackson, Jerome (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C438S108000, C438S112000, C438S118000

Reexamination Certificate

active

06503776

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a stacked chip package, and more specifically to packaging semiconductor chips on a substrate in a stacking arrangement.
2. Description of the Related Art
With ever increasing demands for miniaturization and higher operating speeds, multi-chip modules (MCMs) are increasingly attractive in a variety of electronics. MCMs which contain more than one chip can help minimize the system operational speed restrictions imposed by long printed circuit board connection traces by combining, for example, the processor, memory, and associated logic into a single package. In addition, MCMs decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common MCM is the “side-by-side” MCM. In this version two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. The side-by-side MCM, however, suffers from a disadvantage that the package efficiency is very low since the area of the common substrate increases with an increase in the number of semiconductor chips mounted thereon.
Therefore, U.S. Pat. No. 5,323,060 teaches a multichip stacked device (see
FIG. 1
) comprising a first semiconductor chip
110
attached to a substrate
120
and a second semiconductor chip
130
stacked atop the first semiconductor chip
110
. The chips
110
,
120
are respectively wire bonded to the substrate
120
. U.S. Pat. No. 5,323,060 is characterized by using an adhesive layer
140
between the two chips to provide clearance between the chips for the loops of the bonding wires
150
. The adhesive layer has a thickness greater than the loop height defined by the distance between the active surface of the chip
110
and the vertexes of the outwardly projecting loops of the bonding wires
150
so as to prevent the bonding wires
150
from contacting the chip
130
. The normal loop height is generally about 10 to 15 mils. As thinner packages have been developed, the loop height has been reduced with conventional bonding techniques down to about 6 mils in height by changes in the loop parameters, profile and wire types. However, this loop height is considered to be a minimum obtainable loop height as attempts to go lower have caused wire damage and poor wire pull strengths. Therefore, using this conventional bonding technique, the adhesive layer
140
must have a thickness of at least 8 mils to prevent the bonding wires
150
from contacting the chip
130
. Typical materials for the adhesive layer
140
include epoxy and tape. However, it is very difficult to form an epoxy layer with a stable bond line thickness above 3 mils. Further, even using a tape with a thickness of 8 mils, it will increase the cost of the final product, and the reliability of resulted package will suffer from the CTE mismatch between thermoplastic tape and silicon chip.
Therefore, the semiconductor industry develops a stacked chip package
200
(see
FIG. 2
) characterized by using a dummy chip
160
to provide clearance between the chips for the loop of the underlying bonding wire. The dummy chip
160
is interposed between the chips
110
,
130
via two adhesive layers
162
,
164
. Typically, the adhesive layers
162
,
164
are formed from thermosetting epoxy material. Since it is not easy to control the bond line thickness of epoxy adhesive, a vision system is used to monitor the bond line thickness of the adhesive layer
164
after the chip
130
is bonded to the dummy chip
160
thereby assuring the bonding reliability. But currently the vision system is unable to measure the bond line thickness of the adhesive layer
164
since the chip
130
hinders the vision system from measuring. Once the bond line thickness is not under control, it will introduce unsatisfactory coplanarity after mounting the chip
130
.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a method for fabricating a stacked chip package which overcomes, or at least reduces the above-mentioned problems of the prior arts.
The method for fabricating a stacked chip package in accordance with the present invention comprises the steps of: (a) attaching a lower chip to means for supporting chips, the supporting means being provided with a structure for making external electrical connection; (b) electrically coupling the lower chip to the structure for making external electrical connection; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the structure for making external electrical connection; and (g) encapsulating the lower chip and the upper chip against a portion of the supporting means with a molding compound.
It is far easier to control the thickness of the film adhesive layer than the bond line thickness of the epoxy adhesive. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.


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