Method for fabricating stacked capacitors in a DRAM cell

Fishing – trapping – and vermin destroying

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437 47, 437 48, 437 60, 437228, 437233, 437918, H01L 2170

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active

051048213

ABSTRACT:
A method for fabricating a capacitor in a substrate on which there is prepared a field oxide layer, a gate electrode, a source region, a drain region and an insulation layer, includes the sequential processes of: etching a first mask pattern formed on a portion of a first conductive layer in contact with the source region; forming sequentially a first illustration layer and a second conductive layer on a surface of the first conductive layer; forming on a second conductive layer a second mask pattern having a reverse phase of the first mask pattern; etching the second conductive layer disposed on a portion of the first conductive layer; etching the oxidized second conductive layer disposed on an upper surface of the first insulation layer in a high pressure diffusion furnace; etching anistrophically the first insulation layer by using the oxidated second conductive layer as a mask; forming a pattern for an underlying electrode by etching anistrophically the first conductive layer to a predetermined thickness; removing the oxidated second conductive layer and said first insulation layer, sequentially; and forming a second insulation layer on the surface of the underlying electrode and covering a third conductive layer over the substrate so as to form an upperlying electrode.

REFERENCES:
patent: 4882289 (1989-01-01), Moriuchi et al.
Watanabe et al., "Stacked capacitor cells for High-density DRAMS" IEDm 1988, pp. 600-603.

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