Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-11-08
2001-06-05
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S424000, C438S427000
Reexamination Certificate
active
06242320
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method for fabricating a silicon-on insulator (SOI) wafer, and more particularly to a method for fabricating a SOI wafer capable of improving uniformity of a semiconductor layer where a device is to be formed.
With high integrity and high performance of semiconductor devices, the semiconductor integration technology using SOI wafers instead of single crystal Si wafer being comprised of a bulk silicon has been proposed. It is because the devices fabricated into the SOI wafer has advantages of high speed due to low junction capacitance, low voltage driving due to low threshold voltage and decrease in latch-up due to complete device isolation as compared with those fabricated in the single crystal Si wafer. The SOI wafer has a stack structure of a base substrate for supporting means, a semiconductor layer for providing an active region and a buried oxide layer for a bonding medium sandwiched between the base substrate and the semiconductor layer.
There are a separation by implanted oxygen (SIMOX) method and a bonding method as a SOI wafer fabrication method. The SIMOX method fabricates a SOI wafer having a stack structure of a base substrate, a buried oxide layer and a semiconductor layer by implanting oxygen ions into a Si wafer and forming the buried oxide in a selected depth from the surface of the Si wafer so as to separate the Si wafer into the base substrate and the semiconductor layer with a heat treatment for reacting the oxygen ions and Si. The bonding method fabricates a SOI wafer having a stack structure of a base substrate, a buried oxide layer and a semiconductor layer by bonding two substrates, for example the base substrate and a semiconductor substrate with interleaving the buried oxide layer formed in any one of two substrates and polishing the semiconductor substrate by a selected thickness to form the semiconductor layer where a device is to be formed.
However, the SIMOX method forms the SOI wafer with an ion implantation so that it is difficult to control a thickness of the semiconductor layer where a device is to be formed and it takes a long time for process. Recently, the bonding method is typically used to fabricate the SOI wafer. Because the bonding method can form the isolation layer in the semiconductor layer during the SOI wafer process, it has an additional advantage of exclusion of the isolation process in a device process.
FIG. 1A
to
FIG. 1D
are sectional views illustrating a method for fabricating a SOI wafer in the prior art. Referring to
FIG. 1A
, a base substrate
1
is prepared and a first oxide layer
2
is formed on one surface of the base substrate
1
. The first oxide layer
2
is comprised of a thermal oxide layer formed by a thermal oxidation. Referring to
FIG. 1B
, a semiconductor substrate
3
being comprised of bulk Si is prepared and an isolation layer
4
of a trench type is formed in one surface of the semiconductor substrate
3
. The isolation layer
4
is formed by forming a trench in a selected depth from the surface of the semiconductor substrate
3
and filling the trench with an oxide layer. The isolation layer
4
is used to define an active region and serves as a polishing stopper. A second oxide layer
5
is formed over the one surface of the semiconductor substrate
3
including the isolation layer
4
.
Referring to
FIG. 1C
, the base substrate
1
and the semiconductor substrate
3
are bonded to contact the first oxide layer
2
with the second oxide layer
5
. Referring to
FIG. 1D
, another surface of the semiconductor substrate
3
is polished with a chemical mechanical polishing (CMP) method using the isolation layer
4
as a polishing stopper to form a semiconductor layer
3
a
so that a SOI wafer
10
is fabricated, which comprises the base substrate
1
, the semiconductor layer
3
a
having the isolation layer
4
and the buried oxide layer
6
including the first and second oxide layers
2
and
5
.
In the SOI wafer, uniformity of the semiconductor layer works as an essential factor to characteristic of the semiconductor devices fabricated in the SOI wafer. Because the semiconductor layer provides an active layer where a device is to be formed, it should maintain a thickness of the semiconductor layer to be uniform.
However, the prior method for fabricating the SOI wafer can not provide the semiconductor layer having an uniform thickness. That is, when the another surface of the semiconductor layer is polished using the isolation layer as a polishing stopper to form the semiconductor layer, the dishing that the height at the central portion of the semiconductor layer is lowered than that at the peripheral portion of the semiconductor layer is caused by selectivity between the oxide layer and the silicon layer so that the uniform thickness can not be obtained. Therefore, the device which is formed in the semiconductor layer having a nonuniform thickness has a poor characteristic.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a SOI wafer capable of improving uniformity of a semiconductor layer in a thickness.
According to an aspect of the present invention, there is provided to a method for fabricating a SOI wafer, comprising the steps of: preparing a base substrate and a semiconductor substrate; forming a first insulating layer on the base substrate; forming first isolation layers of trench types having a first depth in one surface of the semiconductor substrate; forming second isolation layers of trench types having a second depth in the one surface of the semiconductor substrate between the first isolation layers, the second depth being deeper than the first depth; forming a second insulating layer over the one surface of the semiconductor substrate including the first and second isolation layers; bonding the base substrate and the semiconductor substrate to contact the first insulating layer with the second insulating layer; firstly polishing another surface of the semiconductor substrate to expose the second isolation layers using the second isolation layer as a polishing stopper; etching the second isolation layers to have the same depth as the first isolation layers; and secondly polishing the first polished another surface of the semiconductor substrate using the first isolation layers and etched second isolation layers as polishing stoppers to form a semiconductor layer.
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Blum David S
Bowers Charles
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
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