Method for fabricating shallow trench isolation layer of...

Details Method for fabricating shallow trench isolation layer of... Method for fabricating shallow trench isolation layer of...

2005-07-07

2008-05-13

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

C438S479000, C438S584000, C438S633000, C257SE21090, C257SE21092, C257SE21102

Reexamination Certificate

active

07371665

ABSTRACT:
A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by minimizing an isolation area between moat areas, which includes the steps of forming a sacrificial layer on a substrate; forming a moat pattern by coating a photoresist on the sacrificial layer and performing exposure and development process to the coated photoresist with a mask pattern of the STI layer; patterning the sacrificial layer by using the moat pattern as a mask; forming an insulating layer on an entire surface of the substrate including the patterned sacrificial layer after removing the moat pattern; forming insulating layer sidewalls at the side of the sacrificial layer by anisotropically etching the insulating layer; removing the sacrificial layer and forming a silicon layer on the substrate; and planarizing the surface of the silicon layer and the insulating layer sidewalls by CMP.

REFERENCES:
patent: 6200866 (2001-03-01), Ma et al.
patent: 2002/0011629 (2002-01-01), Chan et al.
patent: 2005/0001273 (2005-01-01), Bryant et al.
patent: 2005/0090066 (2005-04-01), Zhu et al.
patent: 2005/0133830 (2005-06-01), Diaz et al.
patent: 2005/0136588 (2005-06-01), Speyer
patent: 2005/0170659 (2005-08-01), Hanafi et al.

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