Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1999-06-17
2000-12-19
Pham, Long
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438660, 438663, 438664, 438683, H01L 213205
Patent
active
061627135
ABSTRACT:
Several processes for forming semiconductor gate structures having treated titanium silicide layers are disclosed. There are at least three methods been provided for the present invention and a summarized general procedure of all the methods comprises the following steps: The first step is to provide a silicon substrate having a gate oxide layer formed on top the silicon substrate, and forming a polysilicon layer over the gate oxide layer, followed by the formation of a TiN layer over the polysilicon layer. A treated titanium silicide layer is then formed on top of the TiN layer. Sequentially, an anti-reflection (SiON) film is deposited on top of the treated titanium silicide layer with a capping layer formed over the anti-reflection film. Finally, patterning and etching the above layers to expose a portion of the gate oxide layer and to form a gate electrode, where the final gate structure is rounded up by a rapid thermal process (RTP). The step of forming a treated titanium silicide layer further comprises one of the following: impurity doping by implantation, sputtering with nitrogen gas, and using TiSi.sub.x M.sub.y target. As a result of this, a wider thermal-stress window has been achieved by the present invention.
REFERENCES:
patent: 5170242 (1992-12-01), Stevens et al.
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5576228 (1996-11-01), Chen et al.
patent: 5600165 (1997-02-01), Tsukamoto et al.
patent: 5608266 (1997-03-01), Agnello et al.
patent: 5851922 (1998-12-01), Bevk et al.
patent: 5880502 (1999-03-01), Lee et al.
patent: 5903053 (1999-05-01), Iikima et al.
patent: 5972763 (1999-10-01), Chou et al.
Chen Haber
Chen Li-Yeat
Shieh Wen-Yi
Pham Long
United Microelectronics Corp.
LandOfFree
Method for fabricating semiconductor structures having metal sil does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor structures having metal sil, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor structures having metal sil will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-270816