Method for fabricating semiconductor devices that prevents patte

Details Method for fabricating semiconductor devices that prevents patte Method for fabricating semiconductor devices that prevents patte

1989-04-25

1992-07-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437225, 437226, 148DIG28, H01L 2100, H01L 2102, H01L 2178, H01L 21316

Patent

active

051322528

ABSTRACT:
A method for preventing contamination caused by residues of etched off patterns etched by photolithographic etching. A considerable amount of small contamination spots on a semiconductor chip are found to be caused by tiny residues of etched off patterns. These residues are formed primarily around the periphery of device areas and mark patterns when their outsides are etched off. The occurence of such residues of etching is increased by anisotropic etching. These residues are dislodged by succeeding steps of the pattern making process, and disperse over the substrate causing small contamination spots. To avoid the detrimental effects of the etching residues, the edges of the mark patterns and device areas are covered with an edge cover which is formed in a step to following the pattern etching process.

REFERENCES:
patent: 4179794 (1979-12-01), Kosugi et al.
patent: 4306351 (1981-12-01), Ohsaka et al.
"Improvement of D Level Auto-Align Target Through Redesign of B Level Mask", IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, p. 1788.

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