Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-10-01
2001-01-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S197000, C438S671000, C438S952000
Reexamination Certificate
active
06171940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating semiconductor devices, and more particularly, relates to a photoresist shrink process and an organic material layer having low dielectric constant. The present invention is capable of making gate structures having small dimensions, and in providing semiconductor devices with low production cost.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of the integrated electronic circuit. In particular, as more than hundreds or thousands of electrical components are integrated into the ICs, means for scaling down the dimension of the MOSFET and for reducing fabrication costs has become imperative.
In logic product applications, the smaller the gate structure the faster the handling speed and the higher the integrity of semiconductor devices. Therefore, the production of gate structures having small dimension will be the most important trend in the present day. For the conventional semiconductor devices, when the optical resolution is required to achieve gate structures with small dimension, the size of gate electrodes need to be smaller and smaller, also the thinner the more exposed, and the photoresist layer needs to be thin comparatively. This thin photoresist layer might not be thick enough for blocking the etching process in the follow-up fabrication, hence, is not able to be used in the etching process.
Consequently, semiconductor devices with small dimensions and low production cost are desired urgently.
SUMMARY OF THE INVENTION
In accordance with the present invention, using fluorocarbon/oxygen/helium (C2F6/O2/He) gas mixture for forming a shrunken photoresist layer carries out a photoresist shrink process. Moreover, the present invention can solve this thin photoresist layer which might not be thick enough for blocking the etching process in the follow-up fabrication. A method is provided for forming semiconductor devices with a photoresist shrink process and that substantially produces semiconductor devices with small dimension and at low production cost.
Another object of the present invention is to provide a semiconductor device
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, wherein the organic material layer having low dielectric constant on top of the polysilicon layer is used for a the purpose analogous to a hard mask. Moreover, this organic material layer is also very easy to be removed by using a dry etching method.
A further object of the present invention is to provide a semiconductor device which uses the photoresist shrink process to decide the size of the gate electrode. The present invention can fabricate gate structures having small dimensions, and hence provide a highly integrated semiconductor device.
In accordance with the above objects, a method for fabricating gate structures having small dimension comprises the following steps: Firstly, providing a semiconductor device having a semiconductor substrate therein, then forming a gate oxide layer and a polysilicon layer over the semiconductor substrate one after another Next, depositing a dielectric layer over the polysilicon layer, forming an anti-reflection layer over the dielectric layer, and forming a photoresist layer over the anti-reflection layer for defining the location of a gate electrode. Consequentially, using the photoresist layer as a mask for etching the anti-reflection layer and carrying out a photoresist shrink process, where the dielectric layer is also etched partially, thereafter using the photoresist layer as a mask for etching the dielectric layer, accompanying that, the photoresist layer is also etched partially. After these steps, using the photoresist layer as a mask for etching the polysilicon layer till a surface of said gate oxide layer is exposed, accompanying that, the photoresist layer and the anti-reflection layer are removed within the above etching process, and finally, removing the dielectric layer that is on top of said polysilicon layer.
REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 5656523 (1997-08-01), Wilhoit
patent: 5753557 (1998-05-01), Tseng
Dang Trung
Harness & Dickey & Pierce P.L.C.
United Microelectronics Corp.
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