Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-07-07
2004-10-05
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S291000, C438S962000
Reexamination Certificate
active
06800511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device with negative differential conductance or transconductance, and more particularly, to a method for fabricating a semiconductor device exhibiting negative differential conductance or transconductance at room temperature by using P+-N+ junction barriers, formed by implanting impurity ions into the channel region so that their density is higher than the effective density of states where electrons or holes can exist, and to fabrication processes thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate.
2. Description of the Prior Art
Complementary metal oxide semiconductor (hereinafter, referred to as ‘CMOS’) devices have occupied most of the semiconductor markets as key elements of silicon semiconductor devices which have been continuously scaled down or miniaturized for the purpose of high performance and high integration thereof.
However, it is expected that such continuous miniaturization shall further aggravate problems related to quantum mechanics and statistical mechanics of the devices, and the operation and miniaturization thereof shall reach the limit in the near future due to these problems.
Accordingly, in order to overcome the limit resulting from the miniaturization of the CMOS devices, studies on new nano functional devices are required.
However, in virtue of a great advantage of the CMOS devices, they will continue to be used together with the new nano functional devices for a while. Thus, studies on hybrid integrated circuits should be continued.
Therefore, in view of the studies on the nano devices to be utilized in the near future, active studies on advanced or next generation nano functional devices based on silicon CMOS technologies have been made.
At present, a single electron transistor (SET), which is one of the nano functional devices proposed so far, is a device having the greatest potential for succeeding to metal oxide semiconductor field effect transistor (hereinafter, referred to as ‘MOSFET’).
Since movement of each electron can be adjusted at a lower voltage in the single electron transistor having a nanometer-scale quantum dot between two adjacent tunnel junctions, the single electron transistor can be driven at a lower power and the operation characteristic thereof can be improved according to the miniaturization of the device. Thus, there are advantages in that the SET has a potential for solving difficult problems involved in the existing classical devices and is the most compatible with the silicon based technology, as a current leading technology.
However, the SET should be able to be still operated at room temperature for its practical use. To this end, a technology for reproducibly forming quantum dots of several to several tens nm at desired points is required.
In addition to the single electron device, there is another device using quantum mechanical tunneling at a junction, which is a silicon device serving as the nano functional device.
FIG. 1
shows a basic structure of a device using a silicon tunnel junction and an energy band of the device in a thermal equilibrium state. The device was proposed by L. Esaki in Japan in 1976 for the first time. However, since the Esaki's tunnel junction device is basically a two-terminal device, the device has a problem in view of the active operation thereof.
FIG. 2
is a graph showing the current-voltage characteristic of the device shown in FIG.
1
. If N-type and P-type silicons, each of which has a high density of impurity ions, are joined with each other and a voltage applied thereto is increased in the forward direction, the device exhibits a characteristic of negative differential conductance or transconductance. Further, the device has an advantage in that the characteristic of negative differential conductance or transconductance can be realized even at room temperature regardless of its size.
FIG. 3
is a perspective view of a conventional silicon surface junction tunneling device. A buried oxide film
11
is formed on a silicon substrate
10
, and source
12
and drain
13
are formed in such a manner that they are spaced apart from each other on the buried oxide film
11
.
A gate
16
is formed on the drain
13
with a gate oxide film
15
interposed therebetween. Thus, the device is in the form of a three-terminal active device, in which an inversion layer, i.e. a channel
14
is formed between the N+ source
12
and the P+ drain
13
when a gate voltage Vg is applied to the gate.
Reference numeral ‘
17
’ in the figure designates a field oxide film.
FIG. 4
is a graph showing the characteristic of differential conductance or transconductance with respect to the drain voltage of the device shown in FIG.
3
. Particularly, this figure shows the characteristic of negative differential conductance or transconductance at room temperature.
In case of the three-terminal silicon surface junction tunneling device, impurity ions having opposite polarities should be implanted into the source and drain, respectively. Thus, the process becomes complex and there has been a difficulty in miniaturizing the device.
In the meantime, the methods of fabricating the single electron transistors, which have been made public heretofore, have been implemented through an accidental method for its operation at room temperature, i.e. using of the polysilicon grain, the ununiformity of E-beam lithography, or the potential variation depending on undulation of a thin SOI film of several nm. However, they have the problem of poor reproducibility.
Further, a method of fabricating the single electron transistor by an atomic force microscope (AFM) or a scanning tunneling microscope (STM) has a slow process rate, lacking suitability for mass production.
Moreover, although the method of forming quantum dots by using an oxidation process depending on a pattern has no problems in reproducibility and mass production, there have been disadvantages in that the single electron transistor with the quantum dot formed therein operates only at a lower temperature of about 40 K, and it is difficult to reduce the area occupied by the whole device due to a relatively large upper gate and side electrodes, which are not in a self-aligned structure.
SUMMARY OF THE INVENTION
Accordingly, the present invention is made to solve the above problems in the prior art. An object of the present invention is to provide a method for fabricating a semiconductor device with negative differential conductance or transconductance at room temperature by using P+-N+ junction barriers, formed by implanting impurity ions into the channel region so that their density is higher than the effective density of states where elections or holes can exist, and to fabrication processes thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate.
Another object of the present invention is to provide a method for fabricating a semiconductor device wherein the characteristics of a single electron transistor can be obtained by using a channel region as a quantum dot and two P+-N+ junctions existing between source and drain regions and the channel region as tunneling barriers.
According to an aspect of the present invention for accomplishing the objects, there is provided a method for fabricating a semiconductor device with negative differential conductance or transconductance, which comprises a first step of etching a single crystal silicon layer of an SOI substrate consisting sequentially of a silicon support, a buried oxide film and the single crystal silicon layer so as to form source and drain regions which are spaced apart from each other and a channel region which is connected with the source and drain regions and has a fine line width; a second step of implanting impurity ions into the source, channel and drain regions with their density being higher than the effective density of states at which electrons or holes can exist so that the channel region is dope
Kim Kyung Rok
Lee Jong Duk
Park Byung Gook
Chaudhari Chandra
Dilworth & Barrese LLP.
Seoul National University Industry Foundation
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