Coating processes – Direct application of electrical – magnetic – wave – or... – Chemical vapor deposition
Reexamination Certificate
2001-12-21
2004-02-17
VerSteeg, Steven H. (Department: 1753)
Coating processes
Direct application of electrical, magnetic, wave, or...
Chemical vapor deposition
C204S192150, C427S250000, C427S404000, C438S758000, C438S761000, C438S763000
Reexamination Certificate
active
06692795
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a device for fabricating a semiconductor device, and more particularly, to a method and a device for fabricating a semiconductor device having a ruthenium layer.
2. Description of the Related Art
Recently, efforts have been made to obtain larger capacitance values in capacitors of semiconductor device using noble metals such as ruthenium (Ru), platinum (Pt), iridium (Ir), and osmium (Os) as a lower electrode or an upper electrode of a capacitor. Among the noble metals, ruthenium has excellent leakage current characteristics and easier processing characteristics.
A conventional method for forming a ruthenium layer is by sputtering. The ruthenium layer formed by sputtering has a dense structure and good surface morphology, thereby generating excellent leakage current characteristics and sheet resistance. But the ruthenium layer formed by sputtering has poor step coverage characteristics. It is therefore difficult or not suitable to form three-dimensional structures such as cylindrical or fin shaped electrodes.
Another method for forming a ruthenium layer is chemical vapor deposition (CVD). The ruthenium layer formed by the CVD has good step coverage, but poor surface morphology; therefore, such layer does not have good leakage current and sheet resistance characteristics.
Accordingly, a need exists for a method of fabricating a ruthenium layer having excellent leakage, surface morphology and step-coverage characteristics.
Japan patent application publication No. 11-340435 proposes a method to improve surface morphology and step coverage characteristics, and to reduce deposition time. The method includes the steps of forming a ruthenium seed layer by sputtering, and a ruthenium main layer by CVD. But the layer doesn't have good lateral surface morphology as shown in FIG.
1
.
A conventional method of forming a ruthenium layer is illustrated by
FIGS. 2A
,
2
B, and
3
.
Referring to
FIG. 2A
, a silicon oxide layer
22
having an opening region is formed on a semiconductor substrate
20
. A ruthenium layer
24
having a ruthenium seeding layer by sputtering and a ruthenium main layer by CVD is formed on the silicon oxide
15
layer
22
and inside of the opening region. The inside of the opening region is filled with an Insulating material
26
such as a silicon oxide to completely cover the ruthenium layer
24
. The top surface of the insulating material
26
and the top surface of the ruthenium layer
24
are removed by process such as etch back or chemical mechanical polishing (CMP) until the surface of the silicon oxide layer
22
is exposed, thereby forming a
20
recessed ruthenium layer
24
a
and a recessed insulating material
26
a
as shown in FIG.
2
B. To make a cylindrical ruthenium layer, the silicon oxide layer
22
and the recessed insulating material
26
a
are removed by an etchant such as a buffered oxide etchant (BOE). But the morphology of the recessed ruthenium layer
24
a
is not good. The etchant may permeate under the semiconductor substrate
20
, thereby deteriorating the interface between the recessed ruthenium layer
24
a
and the semiconductor substrate
20
and lowering the reliability of the semiconductor device.
Another problem of using a ruthenium layer is that a ruthenium for forming of the ruthenium layer is aggregated during heat treatment after forming a capacitor, thereby exposing under the ruthenium layer and again lowering the reliability of a semiconductor device.
Thus, notwithstanding these above-described methods of forming semiconductor capacitors, there still continues to be a need for improved method for semiconductor capacitors having a ruthenium layer and device for manufacturing the same.
SUMMARY OF THE INVENTION
A method for fabricating a semiconductor device is provided, which includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.
According to a preferred embodiment of the present invention, the first flow rate of oxygen gas is higher than the second flow rate of oxygen gas. The second pressure is greater than the third pressure, the first pressure is in the range from about 0.5 mTorr to about 5 mTorr, the second pressure is in the range from about 10 Torr to about 40 Torr, and the third pressure is in the range from about 0.1 Torr to about 10 Torr. The first flow rate of oxygen gas is in the range from about 10 sccm to about 3,000 sccm.
According to a preferred embodiment of the present invention, an inert gas is further included flowing with the oxygen gas. The flow rate of the inert gas is in the range from about 10 sccm to 2,000 sccm, and the second flow rate of oxygen gas is in the range from about 10 sccm to about 300 sccm.
According to a preferred embodiment of the present invention, the step of forming the first ruthenium layer is performed at a semiconductor substrate temperature of about 100° C. to about 500° C. The step of forming the second ruthenium layer and the step of forming the third ruthenium layer are performed at a semiconductor substrate temperature of about 250° C. to about 450° C. The step of forming the second ruthenium layer is performed at a semiconductor substrate temperature lowered by about 10° C. to about 30° C. than the step of forming the third ruthenium layer. The step of forming the first ruthenium layer, the step of forming the second ruthenium layer, and the step of forming the third ruthenium layer are performed in-situ. The step of forming the second ruthenium layer and the step of forming the third ruthenium layer are performed in a same chamber.
According to a preferred embodiment of the present invention, the step of forming the second ruthenium layer and the step of the forming the third ruthenium layer use a ruthenium containing organometallic compound. The ruthenium containing organometallic compound includes Ru(EtCp)
2
, wherein EtCp denotes ethyl cyclopentadienyl ligand.
An apparatus for manufacturing a semiconductor device is also provided, which includes: a transfer chamber transferring a wafer; a plurality of process chambers connected to the transfer chamber; and a pressure control unit connected to the transfer chamber for controlling pressure therethrough, wherein the plurality of process chambers has at least one chemical vapor deposition (CVD) chamber for CVD and at least one sputtering chamber for sputtering, and the pressure control unit maintains close to a target pressure of the CVD chamber and the sputtering chamber.
An apparatus for manufacturing a semiconductor device is also provided, which includes: a first transfer chamber having a first robot to transfer a wafer; a second transfer chamber having a second robot to transfer the wafer, wherein the second transfer chamber is connected to the first transfer chamber; a sputtering chamber connected to the first transfer chamber; at least one CVD chamber connected to the second transfer chamber; and a pressure control unit connected to the second transfer chamber, wherein the pressure control unit maintains close to a target pressure of the CVD chamber.
REFERENCES:
patent: 5186718 (1993-02-01), Tepman et al.
patent: 5292393 (1994-03-01), Maydan et al.
patent: 6423593 (2002-07-01), Yamamoto et al.
patent: 2002/0030210 (2002-03-01), Matsui et al.
patent: 2002/0047201 (2002-04-01), Suzuki
patent: 0066676 (1999-08-01), None
Park Soon-yeon
Won Seok-jun
Yoo Cha-young
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
VerSteeg Steven H.
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