Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-04-26
2011-04-26
Fulk, Steven J (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S621000, C257S774000, C257SE21597, C257SE23011
Reexamination Certificate
active
07932179
ABSTRACT:
Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.
REFERENCES:
patent: 4906314 (1990-03-01), Farnworth et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5652557 (1997-07-01), Ishikawa
patent: 5994763 (1999-11-01), Ohmuro
patent: 6022797 (2000-02-01), Ogasawara et al.
patent: 6286684 (2001-09-01), Brooks et al.
patent: 6437451 (2002-08-01), Farnworth et al.
patent: 6446933 (2002-09-01), Westmoreland
patent: 6555921 (2003-04-01), Kwon et al.
patent: 6693358 (2004-02-01), Yamada et al.
patent: 6844623 (2005-01-01), Peterson et al.
patent: 6952054 (2005-10-01), Akram et al.
patent: 2002/0185584 (2002-12-01), Westmoreland
patent: 2003/0082847 (2003-05-01), Turner et al.
patent: 2004/0002573 (2004-01-01), Apen et al.
patent: 2004/0056345 (2004-03-01), Gilleo
patent: 2004/0077180 (2004-04-01), Sebald
patent: 2004/0166659 (2004-08-01), Lin et al.
patent: 2005/0009329 (2005-01-01), Tanida et al.
patent: 2005/0095750 (2005-05-01), Lo et al.
patent: 2005/0214673 (2005-09-01), Clark et al.
patent: 2005/0282378 (2005-12-01), Fukunaga et al.
patent: 2006/0001439 (2006-01-01), Akram et al.
patent: 2006/0019420 (2006-01-01), Liao et al.
patent: 2006/0043599 (2006-03-01), Akram et al.
patent: 2006/0046468 (2006-03-01), Akram et al.
patent: 2006/0160274 (2006-07-01), Larson
patent: 2006/0183349 (2006-08-01), Farnworth et al.
patent: 2006/0289307 (2006-12-01), Yu et al.
patent: 2006/0292877 (2006-12-01), Lake
patent: 2007/0032059 (2007-02-01), Hedler et al.
patent: 2007/0073020 (2007-03-01), Watanabe et al.
patent: 2007/0082297 (2007-04-01), Choi et al.
patent: 2007/0284602 (2007-12-01), Chitnis et al.
patent: 2008/0237849 (2008-10-01), Pratt
patent: 2009/0032964 (2009-02-01), Farnworth et al.
patent: 03114232 (1991-05-01), None
patent: 03 227046 (1991-10-01), None
patent: H07-201689 (1995-08-01), None
patent: H07-242860 (1995-09-01), None
patent: 07312374 (1995-11-01), None
patent: H09-165558 (1997-06-01), None
patent: 2000 003993 (2000-01-01), None
patent: 2005-150235 (2005-06-01), None
patent: WO 01/01768 (2001-01-01), None
patent: WO03081653 (2003-10-01), None
patent: WO2006128028 (2006-11-01), None
Wu et al.; A Through-Wafer Interconnect in Silicon for RFICs; Massachusetts Inst. of Technol., Cambridge, MA, USA; Electron Devices, IEEE Transactions on Publication Date: Nov. 2004; vol. 51, Issue: 11; pp. 1765-1771.
Wu et al.; A High Aspect-Ratio Silicon Substrate-Via Technology and Applications; Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation; MIT, Cambridge, MA, USA; Electron Devices Meeting, 2000; IEDM Technical Digest International Publication Date: Dec. 10-13, 2000; pp. 477-480.
De Samber et al.; Through Wafer Interconnection Technologies for Advanced Electronic Devices; Philips Centre for Ind. Technol., Eindhoven, Netherlands; Electronics Packaging Technology Conference, 2004; EPTC 2004; Proceedings of 6thPublication Date: Dec. 8-10, 2004; pp. 1-6.
Polyakov et al.; Comparison of Via-Fabrication Techniques for Through-Wafer Electrical Interconnect Applications; Delft University of Technology, DIMES/ECTM, Delft, The Netherlands; Electronic Components and Technology Conference, 2004. Proceedings. 54thPublication Date: Jun. 1-4, 2004; vol. 2; pp. 1466-1470 vol. 2.
Garrou, P. , “Thin Film Polymeric Materials in Microelectronic Packaging and Interconnect”; Advanced Packaging Materials, 1998 4th International Symposium on Proceedings; Mar. 15-18, 1998; pp. 53-59.
Liang, Z. et al.; “A Chip-Level Process for Power Switching Module Integration and Packaging”; 39th IAS Annual Meeting Conference Record of the Industry Applications Conference, vol. 3; Oct. 3-7, 2004; pp. 1932-1939.
O'Brien, J. et al.; “Advanced Photoresist Technologies for Microsystems”; Micromech. Microeng., vol. 11; pp. 353-358.
Strandjord, A.J.G. et al.; “Photosensitive Benzocyclobutene for Stress-Buffer and Passivation Applications (One Mask Manufacturing Process)”; Microelectron. Res. & Dev., The Dow Chemical Co., Electronic Components and Technology Conference, Proceedings, May 18-21, 1997; pp. 1260-1268.
Wall, R. N. et al.; “A New Four-Level Metal Interconnect System Tailored to an Advanced 0.5-μm BiCMOS Technology”; IEEE Transactions on Semiconductor Manufacturing, vol. 11, Issue 4; Nov. 1998; pp. 624-635.
Farnworth Warren
Oliver Steve
Fletcher Yoder
Fulk Steven J
Micro)n Technology, Inc.
LandOfFree
Method for fabricating semiconductor device having backside... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device having backside..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device having backside... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2691475