Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-06-27
2004-08-31
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S597000, C438S618000, C438S666000, C438S672000, C438S740000, C438S745000, C438S902000, C438S906000, C438S976000
Reexamination Certificate
active
06784084
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device capable of reducing generations of seam when a self-aligned contact (SAC) plug is formed.
DESCRIPTION OF RELATED ART
It is difficult to obtain process margins of a pattern formation process and overlay accuracy through a mere improvement on a level of integration in a semiconductor device. To solve these problems, a self-aligned contact (SAC) process is employed because it is cost-effective owing to a fact that an additional mask is not required for forming a contact hole pattern and the like. Among various schemes of carrying out the SAC process, the most typical scheme is to use a nitride layer as an etch barrier layer.
Also, because of the high level of integration, a contact process for forming an inter-layer contact, e.g., a plug, is employed. For instance, in about 0.15 &mgr;m semiconductor devices, a hole-type contact mask is used in forming a bit line contact or a storage node contact. However, this use of the hole-type contact mask is not sufficient to secure a contact region due to a misalignment occurring during a photo-etching process. Therefore, a method of using different etch selectivity values between two different types of inter-layer insulation layers, e.g., an oxide layer and a nitride layer, is employed to secure the contact region. This method is employed in the aforementioned SAC process.
More specifically to the SAC process for forming a plug, an oxide layer for insulating a space between plugs is first etched to form a plug contact hole. Then, such material as polysilicon is deposited into the contact hole, and a chemical mechanical polishing (CMP) process is performed thereto to fill the polysilicon into the contact hole so that a plug is formed. Also, a T-type plug mask or an I-type plug mask is used in the SAC process for forming the plug.
However, in spite of the advantages of the SAC process, seams are more likely generated when the polysilicon is used as a plug material. The reason for this problem is because of a deterioration of topology caused by an undercut of an insulation layer. For example, the seam usually occurs at a storage node contact plug and a bit line contact plug when they are made of polysilicon.
Also, a chance of the seam generation is much higher at a portion of the insulation layer having a negative slope produced by the undercut of the insulation layer. Particularly, the seam is a main cause for degrading device characteristics. An increase of leakage currents is one example.
FIGS. 1A
to
1
E are cross-sectional views showing a conventional method for forming a SAC plug with use of the SAC process.
Referring to
FIG. 1A
, a plurality of device isolation layers
102
defining active regions
101
are formed in a substrate
100
. A local oxidation of silicon (LOCOS) technique or a shallow trench isolation (STI) technique is employed for forming the device isolation layers
102
. Also, each of the active regions
101
has an elongated elliptical shape when viewed from a top of the substrate
100
. It should be also noted that there are a plurality of the active regions
101
defined by the device isolation layers
102
although they are expressed in a more simple representation for convenience.
A conductive layer
104
A for forming a gate electrode (hereinafter referred to as a gate conductive layer) and a hard mask
104
B for forming the gate electrode (hereinafter referred to as a gate hard mask) are sequentially formed on an entire surface of the substrate structure. Although it is not illustrated, an oxide-based insulation layer for forming the gate electrode (hereinafter referred to as a gate insulation layer) is formed beneath the gate conductive layer
104
A. The gate insulation layer has a thickness in a range from about 50 Å to about 100 Å. Herein, the gate conductive layer
104
A is a single layer or a stacked layer of such materials as polysilicon, tungsten, tungsten nitride or/and tungsten silicide.
The gate hard mask
104
B is made of such material like silicon nitride having a different etch selectivity from a subsequent inter-layer insulation layer
108
shown in FIG.
1
B. Also, the gate hard mask
104
B has a thickness ranging from about 1000 Å to about 2000 Å.
For a lightly doped drain (LDD) structure, a low concentration of impurity ions for a source/drain is implanted into the active regions
101
formed at both sides of the gate electrode
104
. Then, an etch stop layer
106
for forming a spacer for the gate electrode (hereinafter referred to as gate spacer) is deposited on the above entire substrate structure including the gate hard mask
104
B and the gate conductive layer
104
A. As like the gate hard mask
104
B, the etch stop layer
106
is made of nitride having a different etch selectivity from the inter-layer insulation layer
108
shown in FIG.
1
B. At this time, the etch stop layer
106
is deposited to a thickness in a range from about 300 Å to about 1000 Å. However, it is much preferable to deposit the etch stop layer
106
to a thickness of about 500 Å.
A photoresist pattern (not shown) is formed to make a core cell and a peripheral circuit regions opened. A blanket-etch process is then preformed to the etch stop layer
106
by using the photoresist pattern as an etch mask so that the gate spacer is formed at lateral sides of the gate electrode in the core cell and the peripheral circuit regions.
Next, a high concentration of impurity ions is implanted into the active regions
101
formed at both sides of the gate spacer to thereby form transistors in the core cell and the peripheral circuit regions. At this time, the etch stop layer
106
in the core cell array region is not etched to be used as another etch stop layer for the inter-layer insulation layer
108
.
As shown in
FIG. 1B
, the inter-layer insulation layer
108
is formed on the above substrate structure including the etch stop layer
106
. Herein, the inter-layer insulation layer
108
is made of an oxide layer having an excellent gap-fill property for preventing occurrences of a void phenomenon. Also, the inter-layer insulation layer
108
has a thickness ranging from about 3000 Å to about 9000 Å. A preferable deposition thickness of the inter-layer insulation layer
108
is about 5000 Å. Afterwards, a chemical mechanical polishing (CMP) process or a blanket-etch process is performed to planarize the inter-layer insulation layer
108
. The planarized inter-layer insulation layer
108
remains on the gate hard mask
104
B with a thickness T of about 1000 Å.
A photoresist pattern
110
is formed on the inter-layer insulation layer
108
in such a manner that a region
111
for forming a SAC (hereinafter referred to as a SAC region) in the core cell array region is opened. The SAC region
111
can be a storage node contact region, a bit line contact region or a merged contact region obtained by merging the storage node contact region and the bit line contact region together. Herein, the illustrated SAC region is the merged contact region. The merged contact region is formed in a T-shape and includes a partial portion of the active region
101
and that of a non-active region.
In case of the T-shaped merged contact region, the size of the merged contact region is bigger than that of each storage node contact region and bit line contact region itself. As a result of this increased size, it is possible to prevent an etch-stop phenomenon usually occurring when the contact region is small. In addition, compared to a structure taught in an article by Kohyama et al. entitled “A fully printable, self-aligned and planarized stacked capacitor DRAM cell technology for 1 Gbit DRAM and beyond”,
symp. On VLSI. Digest of Technical Papers
, PP. 17-18, (1997), an occupying area of the photoresist pattern increases to thereby improve etch selectivity.
Next, the inter-layer insulation layer
108
and the etc
Kang Hyeok
Lee Min-Suk
Lee Sung-Kwon
Gurley Lynne
Jacobson & Holman PLLC
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