Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2007-09-18
2007-09-18
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C257S047000, C216S048000
Reexamination Certificate
active
11172190
ABSTRACT:
A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2performed at an energy level of 10˜100keV.
REFERENCES:
patent: 5518941 (1996-05-01), Lin et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5856226 (1999-01-01), Wu
patent: 5960270 (1999-09-01), Misra et al.
patent: 6001695 (1999-12-01), Wu
patent: 6024887 (2000-02-01), Kuo et al.
patent: 6114206 (2000-09-01), Yu
patent: 6169315 (2001-01-01), Son
patent: 6180468 (2001-01-01), Yu et al.
patent: 6214677 (2001-04-01), Lee
patent: 6245618 (2001-06-01), An et al.
patent: 6319807 (2001-11-01), Yeh et al.
patent: 6406963 (2002-06-01), Woerlee et al.
patent: 6518113 (2003-02-01), Buynoski
patent: 6562687 (2003-05-01), Deleonibus et al.
patent: 2005/0196947 (2005-09-01), Seo et al.
patent: 1999-0081482 (1999-11-01), None
C.C. Wu, C.H. Diaz, B.L. Lin, S.Z. Chang, C.C. Wang, J.J. Liaw, C.H. Wang, K.K. Young, K.H. Lee, B.K. Liew and J.Y.C. Sun: Ultra-Low Leakage 0.16μm CMOS for Low-Standby Power Applications; IEDM 99; 1999, pp. 28.2.1-28.2.4; IEEE.
Sang-Hun Seo, Won-Suk Yang, Han-Sin Lee, Moo-Sung Kim, Kwang-Ok Koh, Seung-Hyun Park and Kyeong-Tac Kim: A Novel Double Offset-Implanted Source/Drain Technology for Reduction of Gate-Induced Drain-Leakage with 0.12μm Single-Gate Low-Power SRAM Device; IEEE Electron Device Letters; Dec. 2002; pp. 719-721; vol 23, No. 0.: IEEE.
Naruhisa Miura, Yuji Abe, Kohei Sugihara, Toshiyuki Oishi, Taisuke Furukawa, Takumi Nakahata, Katsuomi Shiozawa, Shigemitsu Maruno and Yasunori Toduka; Junction Capacitance Reduction Due to Self-Aligned Pocket Implantation in Elevated Source/Drain NMOSFETs; IEEE Transactions on Electron Devices, Sep. 2001; pp. 1969-1974; vol. 46, No. 9.: IEEE.
Dang Phuc T.
Dongbu Electronics Co. Ltd.
Fortney Andrew D.
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