Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

2001-10-26

2004-05-04

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S542000, C438S514000, C438S289000, C438S306000, C438S301000

Reexamination Certificate

active

06730583

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating semiconductor devices; more particularly, to an ion implantation and thermal treatment for forming a source/drain of transistor.
DESCRIPTION OF THE RELATED ART
Semiconductor memory devices comprise many metal oxide semiconductor (MOS) transistors, and the characteristics of semiconductor devices depend on the characteristics of MOS transistors. Ion implantation for forming source/drains is an important process determining the characteristics of the MOS transistors even though most processes for fabricating semiconductor devices effect characteristics of the MOS transistor.
Hereinafter, a conventional method for forming a MOS transistor will be described in detail.
Referring to
FIG. 1A
, a shallow trench isolation (STI) process is performed to form an isolation layer
2
in a silicon substrate
1
, ion implantation processes are performed to form a p-well (not shown) and n-well
3
in silicon substrate
1
. Thereafter, a gate oxide
4
and a gate electrode
5
are formed on silicon substrate
1
. A mask oxide
6
and a spacer
7
are formed on an upper surface and sidewalls of gate electrode
5
, respectively. Spacer
7
comprises oxide
itride films, the symbol “/”, as used herein when describing films, defines a layering of films, so that oxide
itride films are a layer of an oxide film overlying a nitride film. On mask oxide
6
, a photo-resist pattern
8
is formed to expose a p
+
source/drain region.
Referring to
FIG. 1B
,
73
Ge ions are implanted in the p
+
source/drain region to form an amorphous layer (not shown) by using photo-resist pattern
8
as an ion implantation mask, and
11
B ions are implanted in the p
+
source/drain region. Thereafter, the photo-resist pattern
8
is removed, n
+
source/drain regions (not shown) are formed, and then subsequent processes for forming MOS transistors are performed. Reference numeral “
9
” in
FIG. 1B
denotes the p
+
source/drain formed by a thermal treatment following ion implantation. The amorphous layer, formed by the
73
Ge ion implantation prior to the
11
B ion implantation, prevents channeling. In some processes,
73
Ge ion implantation for forming the amorphous layer is skipped by implanting
49
BF
2
ions instead of
11
B ions since the molecular weight of the
49
BF
2
ion is large enough to form an amorphous layer.
As the integration of semiconductor devices increase, the contact size decreases and the contact resistance increases. Therefore, additional ions are implanted in the source/drain region under the contact holes in order to reduce contact resistance during the processes for forming bit line contact or metal-wire contact. Specially, additional
49
BF
2
ions are implanted in the p
30
source/drain region because the solid solubility of a p-type dopant like
11
B in a silicon crystal is lower by one-order of magnitude (one-order being 10
−1
) than that of an n-type dopant like
31
P or
75
As, at the same temperature.
In case of implanting additional
49
BF
2
ions, the contact resistance may be reduced, however the extent of the reduction is not so much due to the low solid solubility of
11
B ions in the silicon crystal. Moreover, the end of range (EOR) defects, induced by interstitial diffusion as a result of the additional ion implantation, cause leakage current.
The dosage of F ions is always two times as much as that of B ions when
49
BF
2
ions are implanted. The F ion prevents the B ion from transient enhanced diffusion (TED), so that it is possible to obtain shallow junctions. However, in case that the dosage of F ions is excessive, the F ions interfere with the activation of B ions causing an increase in the contact resistance.
FIG. 2
shows thermal treatments performed after the ion implantation for forming source/drain. A source/drain rapid thermal annealing (RTA) for activating dopants in the source/drain is performed at temperatures of about 1000° C. The thermal treatments performed after source/drain RTA are carried out at low temperatures in the range of 600° C. to 850° C. depending on the stabilities of subsequent processes, such as a bit line formation process, a capacitor formation process and a metal-wire formation process. However, the dopants in the p
+
source/drain regions are inactivated during the low temperature processes, so that the contact resistance increases. As described in “Wolf, Silicon Processing for the VLSI Era, vol. 1, p. 304”, the dopants in the p
+
source/drain region are inactivated by the dislocations, which are formed easily at low temperature in the range of 600° C. to 850° C., because the dopants are precipitated on or near these dislocations.
FIG. 3
shows isochronal annealing behavior of boron. In
FIG. 3
, the ratio of free-carrier content, P
Hall
, to dose, &phgr;, is plotted against anneal temperature. As shown in
FIG. 3
, the inactivation of the dopants actually increases at temperatures of 600° C. to 700° C.
But, these experimental results show that the temperature for reaching maximum resistance is about 800° C.
FIG. 4
shows the sheet resistance as a function of thermal treatment conditions for p
+
source/drain regions. In
FIG. 4
, ‘RTA(1000° C.-10 s)’ denotes RTA performed at a temperature of 1000° C. for 10 seconds, ‘FA(800° C.-20 s)’ denotes furnace annealing (FA) performed at a temperature of 800° C. for 20 seconds, ‘RTA(850° C.-20 s)’ denotes RTA performed at a temperature of 850° C. for 20 seconds, ‘FA(700° C.-3 h)’ denotes FA performed at a temperature of 700° C. for 3 hours, and ‘FA(800° C.-10 m)’ denotes the FA performed at a temperature of 800° C. for 10 minutes. The thermal treatments shown in
FIG. 4
are performed successively. Referring to
FIG. 4
, the sheet resistance increases on the ‘FA(800° C.-20 s)’ condition (A), this is evidence showing that the inactivation of the dopants actually increase at the temperature of 800° C.
As for the n
+
source/drain regions, the activation of the dopants may be recovered by thermal treatment performed at a temperature of about 850° C., because the solubility of n-type dopants in a silicon crystal is high. However, the activation of the dopants, already inactivated in the p
+
source/drain region, doesn't increase even though the thermal treatment is performed at a temperature of about 850° C.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor memory device fabrication method capable of improving the electrical characteristic of the source/drain region.
The present invention also provides a semiconductor memory device fabrication method capable of improving the electrical characteristic of the p-type source/drain region formed by the implantation of boron ion.
An embodiment of the present invention provides a method for fabricating a semiconductor memory device having a p-type source/drain region, comprising: forming a first amorphous layer in a p-type source/drain region by implanting first dopants including fluorine and boron, implanting second dopants including boron in the first amorphous layer formed in the p-type source/drain region, and forming the p-type source/drain by performing a thermal treatment for activating the first dopants and the second dopants.
Another embodiment of the present invention provides a method for fabricating a semiconductor memory device having a p-type source/drain, comprising: forming an amorphous layer in the p-type source/drain region by implanting first dopants including fluorine and boron, implanting second dopants including boron in the amorphous layer formed in the p-type source/drain region, and performing a plurality of subsequent processes accompanying a thermal treatment, and performing a first rapid thermal annealing process for activating the first dopants and the second dopants.
Another embodiment of the present invention provides a method for fabricating a semiconductor memory device having a p-type source/drain in a silicon substrate, comprising: forming an amorphous layer in a

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