Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2002-12-31
2004-07-27
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C438S289000, C438S301000
Reexamination Certificate
active
06767808
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a method for fabricating a semiconductor device having an improved channel characteristics.
DESCRIPTION OF RELATED ART
As the semiconductor device has been integrated, a channel length becomes to decrease. Although the size of the device becomes to reduce, concentrations of source and drain are still very high to improve a velocity thereof.
A short channel length allows a threshold voltage(V
T
) to fall rapidly as a distance between a source and a drain becomes short. The falling of the threshold voltage(V
T
) increases a leakage current at an atmosphere and generates a punch of the source and the drain to deteriorate the device characteristics. Specifically, in a p-channel metal-oxide semiconductor(PMOS) device major carriers are holes, a mobility of carriers of the PMOS is low 3 times in comparison with that of carrier, i.e., electrons, of an n-channel metal-oxide semiconductor(NMOS). Therefore, controls of concentration and positions of channel dopants and segregation from a field oxidation layer in the channel become very important.
FIG. 1A
is a cross-sectional diagram showing a PMOS device in accordance with a conventional method.
Referring to
FIG. 1A
, an n-type well
13
is formed in a semiconductor substrate
11
formed therein a field oxidation layer
12
as a device isolation layer. A gate oxidation layer
14
and a gate electrode
15
are formed on a selected region on the semiconductor substrate
11
. A p-type channel region
16
is formed below the gate oxidation layer
14
in the semiconductor substrate
11
. And, p-type source/drain regions
17
are formed with adjoining to the p-type channel region
16
in aligning both edges of the gate electrode
15
.
In the prior art shown in
FIG. 1A
, curing defects generated by an ion implantation or an activation of dopants is realized by annealing at a high temperature at one time during a well annealing without an annealing process for an additional electrical activation with respect to the channel regions or by a thermal oxidation process of a gate oxidation layer.
And, after the forming of the p-type source/drain regions
17
, crystal defects necessarily generated during an ion implantation are removed and an annealing process is performed to activate the dopants. At this time, the annealing performed by raising a temperature at a low rising temperature velocity to a maximum process temperature at a time.
But, as shown in
FIG. 1B
, although the crystalline defects can be cured as the annealing process is proceeded at a high temperature during a long time, as a channel size of device becomes to decrease, dopants of the p-type channel regions
16
move into a bottom portion of the n-type well
13
, inactivated dopants in the source/drain regions combine with vacancy to become an intrusion-type defect(x) and the intrusion-type defect(x) is diffused to an end portion of the bottom portion of the gate electrode
15
and the semiconductor substrate
11
in the form of bulk. Since borons as dopants of the p-type channel regions
16
are segregated to the intrusion-type defect(x) and a concentration nonuniformity of dopants is generated in the p-type channel regions
16
, it is difficult to obtain a uniform distribution of dopants in a shallow channel region.
Also, as the device becomes smaller the threshold voltage becomes larger, in order to control this, although a doping concentration of the p-type channel region
16
becomes to increase, since a local annealing process for the p-type channel regions
16
does not implement in a conventional method, there is a problem that a local concentration gradient, i.e., a variation width of the threshold voltage in response to the nonuniformity of the dopants, becomes to increase.
Furthermore, after the formation of the p-type source/drain regions, conditions of annealing for the defect remove and an electrical activation of the impurities has a very high thermal budget in a high density integrated device with a shallow junction and a small size and a maintaining time is nearly ranged from 10 seconds to 20 seconds at a maximum process temperature. Such conditions cause the mobility to be reduced at a surface as diffusions are occurred in a longitudinal direction and a horizontal direction of junction, as a result, a drain saturation current is decreased and a dose of dopants implanted by a dopant diffusion is decreased to thereby reduce a contact resistance.
Therefore, the diffusion of dopants in the implanted channel regions is suppressed by lowering a thermal burden and the uniformity of dopants in the channel regions by preventing the segregation to the field oxidation layer, and also another thermal treatment process is required to recover the crystalline defect layer damaged during the ion implantation to form the source/drain regions and to electrically activate the dopants.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide solve the above-described problems of the conventional method and to provide a method for forming a p-channel metal-oxide semiconductor(PMOS) device suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions.
It is another object of the present invention to provide a method for forming a PMOS device having a shallow junction and a low contact resistance.
It is another object of the present invention to provide a method for forming a PMOS device suitable for minimizing diffusions of channel and source/drain regions and for suppressing a movement of intruding type defects injected by an inactivation of dopants.
In accordance with one aspect of the present invention, there is provided a method for forming a p-channel metal-oxide semiconductor(PMOS) device, the method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.
In accordance with another aspect of the present invention, there is provided a method for forming a PMOS device, wherein each of the first annealing and the second annealing processes are includes a first step for first annealing by a velocity of a first rising temperature to a first process temperature at which a solid phase polycrystalline growth is occurred and a second step for annealing by a velocity of a second rising temperature from the first process temperature to a second process temperature of a maximum process temperature, respectively, wherein the velocity of the second rising temperature is relatively larger than that of the first rising temperature.
In accordance with another aspect of the present invention, there is provided a method for forming a PMOS device, wherein the first process temperature is ranged from 500° C. to 650° C. during the first annealing process and the velocity of the first rising temperature is ranged from 20° C./sec to 50° C./sec.
In accordance with another aspect of the present invention, there is provided a method for forming a PMOS device, wherein during the second annealing the second process temperature is ranged from 650° C. to 900° C.-1050° C. and the velocity of the second rising temperature is ranged from 100° C./sec to 200° C./sec
REFERENCES:
patent: 5955754 (1999-09-01), Azuma et al.
patent: 6066547 (2000-05-01), Maekawa
patent: 6214654 (2001-04-01), Yu
patent: 6225197 (2001-05-01), Maekawa
patent: 6518136 (2003-02-01), Lee et al.
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Nhu David
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