Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-02
2003-12-16
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S725000
Reexamination Certificate
active
06664181
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly, it relates to a method for forming a hole and an interconnect groove respectively for use in forming a plug and a buried interconnect by a dual damascene method.
Recently, there are increasing demands for attaining high performance and refinement of semiconductor integrated circuit devices. Therefore, as a method for increasing the information transfer rate within a semiconductor integrated circuit and improving the reliability of interconnects included in the semiconductor integrated circuit, the dual damascene method using copper as an interconnect material attracts attention.
A method for forming a hole and an interconnect groove in an insulating film for use in forming a plug and a buried interconnect by the dual damascene method is roughly divided into two, one of which is trench-first process for forming the interconnect groove first and the other of which is hole-first process for forming the hole first.
Since a hole is formed after forming an interconnect groove in an insulating film in the trench-first process, it is necessary to perform lithography for forming the hole in a region of the insulating film where the interconnect groove has been formed. At this point, since a level difference derived from the interconnect groove has been caused in a resist film, when the resist film is subjected to pattern exposure for forming the hole, the focus is disadvantageously shifted and hence a fine hole pattern cannot be formed. Accordingly, the hole-first process is preferred for forming a fine hole.
Now, a first conventional method for forming a hole and an interconnect groove by the hole-first process will be described with reference to
FIGS. 12A through 12C
and
13
A through
13
C.
First, as shown in
FIG. 12A
, a lower interconnect
12
is formed in a first insulating film
11
deposited on a semiconductor substrate
10
, and thereafter, a passivation film
13
for preventing corrosion of the lower interconnect
12
is formed from a silicon nitride film with a comparatively large thickness on the first insulating film
11
. The passivation film
13
has a comparatively large thickness because the passivation film
13
works as an etching stopper in two etching procedures described later.
Next, after depositing a second insulating film
14
on the passivation film
13
, a patterned antireflection film
15
and a first resist pattern
16
are formed on the second insulating film
14
. Then, the second insulating film
14
is etched by using the first resist pattern
16
as a mask, so as to form a hole
17
A in the second insulating film
14
. In this etching procedure, the passivation film
13
works as the etching stopper. Thereafter, the first resist pattern
16
and etching residues are removed by ashing and wet cleaning.
Subsequently, as shown in
FIG. 12B
, a second resist pattern
18
is formed on the antireflection film
15
.
Then, the second insulating film
14
is etched by using the second resist pattern
18
as a mask, so as to form an interconnect groove
17
B in the second insulating film
14
as shown in FIG.
12
C. Also in this etching procedure, the passivation film
13
works as the etching stopper. Thereafter, the second resist pattern
18
and etching residues are removed by the ashing, and the substrate is cleaned.
Next, as shown in
FIG. 13A
, the passivation film
13
is etched by using, as a mask, the second insulating film
14
in which the hole
17
A and the interconnect groove
17
B have been formed, so as to expose the lower interconnect
12
.
Then, as shown in
FIG. 13B
, a metal film
19
is deposited on the second insulating film
14
so as to fill the hole
17
A and the interconnect groove
17
B, and a portion of the metal film
19
present above the second insulating film
14
is removed by, for example, CMP. Thus, a plug
19
A and an upper interconnect
19
B made from the metal film
19
are formed as shown in FIG.
13
C.
Now, a second conventional method for forming a hole and an interconnect groove by the hole-first process will be described with reference to
FIGS. 14A through 14C
and
15
A through
15
C.
First, as shown in
FIG. 14A
, a lower interconnect
22
is formed in a first insulating film
21
deposited on a semiconductor substrate
20
, and thereafter, a passivation film
23
for preventing corrosion of the lower interconnect
22
is formed from a silicon nitride film with a comparatively small thickness on the first insulating film
21
. The passivation film
23
has a comparatively small thickness because the passivation film
23
works as an etching stopper in one etching procedure alone as described later. Then, after depositing a second insulating film
24
on the passivation film
23
, a patterned antireflection film
25
and a first resist pattern
26
are formed on the second insulating film
24
. Next, the second insulating film
24
is etched by using the first resist pattern
26
as a mask, so as to form a hole
27
A in the second insulating film
24
. In this etching procedure, the passivation film
23
works as the etching stopper. Thereafter, the first resist pattern
26
and etching residues are removed by the ashing, and the substrate is cleaned.
Next, as shown in
FIG. 14B
, a second resist pattern
28
is formed on the antireflection film
25
, and an organic film
29
made of a resist material or an antireflection film material is buried in the hole
27
A. At this point, in the case where the organic film
29
is made of a resist material, after forming a resist film on the antireflection film
25
so as to fill the hole
27
A, the resist film is patterned, so that the organic film
29
can be buried in the hole
27
A. Alternatively, in the case where the organic film
29
is made of an antireflection film material, after burying the organic film
29
in the hole
27
A, a resist pattern is formed on the antireflection film
25
, so that the organic film
29
can be buried in the hole
27
A.
Next, the second insulating film
24
is etched by using the second resist pattern
28
as a mask, so as to form an interconnect groove
27
B in the second insulating film
24
as shown in FIG.
14
C. In this etching procedure, the organic film
29
protects the lower interconnect
22
. Then, the second resist pattern
28
, the organic film
29
and etching residues are removed by the ashing, and the substrate is cleaned.
Subsequently, as shown in
FIG. 15A
, the passivation film
23
is etched by using, as a mask, the second insulating film
24
in which the hole
27
A and the interconnect groove
27
B have been formed, so as to expose the lower interconnect
22
.
Then, as shown in
FIG. 15B
, a metal film
31
is deposited on the second insulating film
24
so as to fill the hole
27
A and the interconnect groove
27
B, and a portion of the metal film
31
present above the second insulating film
24
is removed by, for example, the CMP. Thus, a plug
31
A and an upper interconnect
31
B made from the metal film
31
are formed as shown in FIG.
15
C.
In the first conventional method, the passivation film
13
has a large thickness in order to prevent the lower interconnect
11
from being damaged during the two etching procedures as described above.
Therefore, the passivation film
13
, which is made from a silicon nitride film with a large dielectric constant and has a large thickness, is provided between the lower interconnect
11
and the upper interconnect
19
B as shown in FIG.
13
C. Accordingly, interconnect capacitance between the lower interconnect
11
and the upper interconnect
19
B is disadvantageously large, which can cause a problem of signal delay.
Furthermore, since the passivation film
13
is largely etched in the etching procedure for exposing the lower interconnect
11
, a damage layer
12
a
is unavoidably formed in the lower interconnect
11
as shown in
FIG. 13A
, which disadvantageously spoils the reliability of the lower interconnect
11
.
Moreover, since the p
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