Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-12-06
2002-05-14
Bowers, Charles (Department: 2827)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S649000, C438S655000, C438S651000
Reexamination Certificate
active
06387789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a polycide gate.
2. Background of the Related Art
Currently, a gate of a semiconductor device of a size below 0.18 &mgr;m class is fabricated by forming a metal gate of tungsten and the like on polysilicon, or by stacking silicide on the polysilicon for forming polycide, particularly, memory cells have gates of metal mostly, logic device uses a dual gate, and a silicide process is generally used. In a case of an embedded memory in which technologies of memory and logic are combined and is a product expected to be paid attention in near future, though a gate structure is newly required, which has interchangeability with both of the two gate structures, employment of the two technologies as they are is difficult. As the salicide technology for a size below 0.18 &mgr;m class is mostly the cobalt salicide technology, it is impossible to obtain an embedded memory by an existing technology because etching of the cobalt salicide material is impossible. Therefore, the cobalt salicide is formed only on a region where the gate electrode is to be formed.
A related art method for forming the aforementioned polycide gate will be explained with reference to the attached drawings. FIGS.
1
A~
1
H illustrate sections showing the steps of a related art method for forming a polycide gate electrode.
Referring to
FIG. 1A
, an active region and a field region are defined on a silicon substrate
1
, and a field oxide film
2
is formed in the field region. As shown in
FIG. 1B
, a gate insulating film
8
, a polysilicon
3
, and an insulating film
4
are formed in succession on an entire surface of the substrate having the field oxide film formed therein. The insulating film
4
is formed of nitride. As shown in
FIG. 1C
, a photoresist film
6
is deposited on the insulating film
4
, and subjected to exposure and development to define a gate electrode pattern region at first. Then, the insulating film
4
on the gate electrode pattern region is removed, selectively. As shown in
FIG. 1D
, cobalt is deposited on an entire surface, and reaction between the cobalt and the polysilicon
3
is caused at a surface of the exposed polysilicon
3
in the gate electrode pattern region, to form polycide
10
. That is, though the polycide is formed at an interface of the cobalt and the polysilicon
3
, no polycide is formed on the insulating film
4
. Therefore the cobalt that made no reaction is removed. In this instance, as the polycide
10
is formed along the polysilicon
3
, the gate electrode pattern region is defined larger than actually required, to cause a defective pattern when the polysilicon
3
is removed in a following process. As shown in
FIG. 1E
, a thick cap insulating film is deposited on an entire surface. As shown in
FIG. 1F
, the cap insulating film
11
is subjected to CMP(Chemical Mechanical Polishing) to remove the cap insulating film
11
until a surface of the first insulating film
4
is exposed. As shown in
FIG. 1G
, the insulating film
4
is removed such that the cap insulating film
11
is left on the gate electrode pattern region. Phosphoric acid is used in removing the insulating film
4
if the insulating film
4
is formed of a nitride. As shown in
FIG. 1H
, the left cap insulating film
11
and the polycide
10
are used as masks in removing the polysilicon
3
selectively, to form a gate electrode, finally.
However, the method for forming a polycide gate electrode has the following problems.
The gate electrode is formed by depositing a nitride film on a polysilicon, exposing a region of the polysilicon on which the gate electrode is to be formed, and forming cobalt silicide only on the region. However, because the cobalt silicide is formed larger than a gate electrode area, uniformity of critical dimensions of gate electrode lengths is deteriorated.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a polycide gate that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a polycide gate which can stabilize uniformity of critical dimensions of gate electrode lengths.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a semiconductor device includes the steps of (1) forming a gate insulating film, a silicon layer, and an insulating film on a substrate in succession, (2) selectively removing a portion of the insulating film on which a gate electrode is to be formed, (3) forming first sidewalls at sides of the insulating film having the portion removed therefrom, (4) forming silicide on a surface of the exposed silicon, (5) forming a cap insulating film on the silicide and the first sidewalls, (6) removing the insulating film, and (7) using the cap insulating film as a mask in removing the exposed silicon layer, to form the gate electrode.
In other aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of (1) forming a gate insulating film, a polysilicon layer, and a first insulating film on a substrate in succession, (2) selectively removing a portion of the first insulating film on which a gate electrode is to be formed, (3) forming second insulating film sidewalls at sides of the first insulating film having the portion removed therefrom, (4) forming silicide on a surface of the exposed polysilicon, (5) forming a cap insulating film on the silicide and the second insulating film sidewalls, (6) removing the first insulating film, and (7) using the cap insulating film as a mask in selectively removing the exposed polysilicon layer, to form the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 5668021 (1997-09-01), Subrmanian et al.
Bowers Charles
Hyundai Electronics Industries Co,. Ltd.
Kebede Brook
Morgan & Lewis & Bockius, LLP
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