Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

2001-05-21

2002-09-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S671000, C438S244000, C438S239000

Reexamination Certificate

active

06448179

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device. In particular, the present invention relates to a method for preventing or significantly reducing the incidents of damaging active regions of a semiconductor substrate comprising a contact plug due to misalignment during its fabrication.
BACKGROUND OF THE INVENTION
Developments in techniques for forming a fine pattern on a semiconductor substrate have led to an increased use of highly integrated semiconductor devices. To form a semiconductor with a fine pattern requires a photoresist film mask with a correspondingly miniaturized pattern for etching and/or ion implantation.
In general, the resolution (R) of a photoresist film pattern is proportional to the light wavelength (&lgr;) and the process variable (&lgr;) of a micro exposure device. The resolution, however, is inversely proportional to the numerical aperture (NA) of the light exposure device, i.e., R=k×&lgr;/NA. Thus, one can improve the resolution (i.e., reduce the value of R) by decreasing the light wavelength, for example, the resolution of G-line (&lgr;=436 nm) and i-line (&lgr;=65 nm) micro exposure devices are about 0.5 &mgr;m and 0.3 &mgr;m, respectively. A photoresist film pattern below 0.3 &mgr;m typically requires a deep ultraviolet (DUV) light exposure device which generates a small wavelength length, for example, a KrF laser (248 nm) or an ArF laser (193 nm).
Other methods for improving the photoresist pattern resolution include using a phase shift mask as a photo mask; using a contrast enhancement layer (CEL) method to form a thin film to enhance an image contrast on a wafer; using a tri-layer resist TLR) method which positions an intermediate layer, such as a spin on glass (SOG) film, between two photoresist films; and using a silylation method to selectively implant a silicon into the upper portion of a photoresist film.
In a highly integrated semiconductor device, typically the size of a contact hole connecting the upper and lower conductive interconnections and the space between the contact hole and the adjacent interconnection are smaller relative to a less integrated semiconductor device. In addition, the aspect ratio of the contact hole in a highly integrated semiconductor device is typically higher than a less integrated semiconductor device. Thus, a highly integrated semiconductor device having a multi-layer conductive interconnection requires a precise mask alignment during its fabrication process, which reduces the process margin, i.e., acceptable error limit. Therefore, to maintain a space between contact holes, in conventional processes masks are formed with consideration to misalignment tolerance, lens distortion in the exposure process, critical dimension variation in the mask formation and photoetching processes, and mask registrations.
A self aligned contact (SAC) method has also been used in a contact hole formation process to overcome some of the disadvantages of lithography processes. The SAC method typically uses a polysilicon, a nitride, or an oxide nitride material as an etch barrier film. Of these, a nitride material is most often used as an etch barrier film.
In a conventional SAC method, a substructure, for example, a device isolation insulation film, a gate insulation film, and a metal-oxide semiconductor field effect transistor (MOSFET) comprising a gate electrode overlapped with a mask oxide film pattern and source/drain regions, is formed on a semiconductor substrate, and an etch barrier film and an interlayer insulation film comprising an oxide are formed over the substructure. A photoresist film pattern of a storage electrode contact and/or a bit line contact is formed by exposing the interlayer insulation film. The resulting interlayer insulation film is dry-etched to expose the etch barrier film. And a contact hole is produced by etching the etch barrier film.
Unfortunately, if the design rule is small, active regions of the semiconductor substrate are exposed during the SAC method due to a resolution deficiency of the lithography process and/or misalignment of the mask. Generally, the photoresist film mask, which is used to protect a presumed contact plug region, cannot cover the entire exposed active regions, and thus the active regions are damaged during the etching process.
One can overcome this limitation by using a sufficiently large photoresist film mask to cover the entire active regions of the semiconductor substrate, and increasing the resulting contact plug size by depositing a polymer. However, particles are generated during the polymer depositing process. These particles deteriorate the yield and the operation property of the device. Thus, a cleaning process is often required to maintain the usefulness of the system resulting in increased cost and time.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device which can prevent or significantly reduce active regions of a semiconductor substrate from being damaged due to misalignment during a contact plug formation process.
One aspect of the present invention provides a method for fabricating a semiconductor device, comprising the steps of:
producing a semiconductor substrate comprising a MOSFET and a device isolation film;
forming a conductive material layer on said semiconductor substrate;
forming a metallic film on said conductive layer, wherein said metallic film is a metal oxide or a metal nitride film;
forming a photoresist film mask on said metallic film for protecting a presumed region of a bit line contact plug and a storage electrode contact plug;
producing an intermediate mask (e.g., combined elements of
23
b
and
25
of
FIG. 2B
) comprising said metallic film using said photoresist film mask;
producing a contact plug mask (e.g., combined elements of
23
b,
25
and
27
of
FIG. 2C
) by coating a polymer comprising a metal on side walls of said intermediate mask;
producing a bit line contact plug and a storage electrode contact plug from said conductive material layer using said contact plug mask; and
removing said contact plug mask.
Preferably, the metallic film is selected from the group consisting of Al
2
O
3
, Ta
2
O
5
, and TiN. In one particular embodiment of the present invention, the polymer which is used to coat the side walls of the intermediate mask comprises a corresponding metal. For example, when the metallic film is Al
2
O
5
, Ta
2
O
5
or TiN, the polymer comprises Al, Ta or Ti, respectively.
Preferably, when the metallic film is Al
2
O
5
or Ta
2
O
5
, the intermediate mask producing step comprises etching the metallic film using a gas mixture comprising:
(i) a fluorine containing gas;
(ii) a halogen gas or a halogen containing gas;
(iii) oxygen or oxygen containing gas; and
(iv) an inert gas.
Preferably, when the metallic film is TiN, the intermediate mask producing step comprises etching the metallic film using a gas mixture comprising:
(i) a halogen gas or a halogen containing gas;
(ii) oxygen or oxygen containing gas; and
(iii) an inert gas.
Preferably, the fluorine containing gas is selected from the group consisting of CF
4
, C
2
F
4
, C
3
F
6
, C
3
F
8
, C
4
F
6
, C
4
F
8
, C
5
F
8
, CHF
3
, CH
2
F
2
,CH
3
F, NF
3
and SF
6
.
Preferably, the halogen gas is Cl
2
.
Preferably, the halogen containing gas is selected from the group consisting of BCl
3
and HBr.
Preferably, the oxygen containing gas is selected from the group consisting of CO
2
, NO and NO
2
.
Preferably, the inert gas is selected from the group consisting of He, Ne, Ar and Xe.
Preferably, the conductive material is selected from the group consisting of a polysilicon, tungsten and Ti/TiN.
Another aspect of the present invention provides a method for fabricating a semiconductor device, comprising the steps of:
forming a semiconductor substrate comprising a MOSFET and a device isolation film;
forming a conductive material layer on said semiconductor substrate;
forming an Al
2
O
3
film on said conductive

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