Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
1999-11-05
2002-01-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S232000, C438S307000, C438S651000
Reexamination Certificate
active
06342441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device which can improve a property of a PN junction formed in a semiconductor substrate by using a silicide as a dopant source.
2. Background of the Related Art
As a junction depth is decreased, undesirable resistances, such as parasitic, shallow depth, or sheet resistances, and contact resistances of source/drain regions are increased more than a channel resistance, which prevents semiconductor devices from being normally operated. A doped polysilicon, tungsten-silicide, polycide or the like are generally used as a material of a gate electrode.
Resistances of very large scale integrated circuits (VLSI) should be minimized, which has been attempted using self-aligned silicide (SALICIDE). However, in a related method of forming the salicide after forming a PN junction, silicon in the junction is consumed when the salicide is formed. As a result, current leakage is high, limiting the effectiveness of the fabrication of a shallow junction.
A well-known junction formation technique which can compensate for the disadvantage of the related salicide formation technique is to use a silicide dopant source (SADS) process disclosed in R. Liu et al., J. Appl. Phys. vol. 63, p. 1990 (1988), the disclosure of which is incorporated herein by reference in its entirety. According to the SADS process, silicide is formed by the salicide process before forming the PN junction. Thereafter, ions are implanted into the silicide, and a thermal process is carried out thereon. A dopant is driven in the silicon at a lower portion from the silicide, thereby forming the junction.
According to the SADS process, damage resulting from the ion implantation occurs merely in the silicide, and does not influence a silicon substrate, but provides a superior junction property. In addition, the silicide junction is formed as rough as a silicide/silicon interface, and thus the silicide passing through the junction does not generate leakage. Furthermore, a dopant concentration at the highly-doped region of the junction is not reduced by the silicide as in the related method, and the dopant concentration at the silicide/silicon interface is maintained, resulting in an improved contact resistance.
In R. Lippens et al., J. Physique C 4, 191 (1988), the disclosure of which is incorporated herein by reference in its entirety, the method of using the silicide as a dopant diffusion source is described for a gate doping of a polysilicon and a junction formation. The Lippens article discloses that it is much easier to perform the gate doping of the polysilicon in a polycide structure by using the silicide as a dopant diffusion source.
It is also described in L. van den Hove et al., Appl. Surf. Sci., vol.38, p.430 (1989), the disclosure of which is incorporated herein by reference in its entirety, that the silicide to which the SADS process can be applied has good reactivity with the dopant, and thus CoSi
2
is preferable to TiSi
2
.
FIGS. 1A
to
1
D are process views illustrating sequential steps of a related method of fabricating a semiconductor device. As shown in
FIG. 1A
, a field oxide film
2
is formed at a device isolation region F
1
of a P-type semiconductor substrate
1
by a local oxidation of silicon (LOCOS) process. A gate insulation film
3
is formed at a device formation region Al of the substrate
1
by performing a thermal oxidation process on the surface of the substrate
1
. A gate electrode
4
is formed on the gate insulation film
3
by depositing the polysilicon by a chemical vapor deposition (CVD) process and patterning the deposited polysilicon layer.
As shown in
FIG. 1B
, sidewall spacers
5
having oxide or nitride are formed at each side wall of the gate electrode
4
and the gate insulation film
3
. A cobalt silicide layer (CoSi
2
)
6
having a thickness of approximately 350 Å is formed on the gate electrode
4
and on the substrate
1
adjacent to both the field oxide film
2
and the side portions of the sidewall spacers
5
. The cobalt silicide layer
6
is formed by depositing a cobalt (Co) layer at an entire surface of the substrate
1
, by performing an annealing process thereon, and by selectively removing the cobalt layer formed on the sidewall spacers
5
and the field oxide film
2
. As illustrated in
FIG. 1C
, arsenic (As), which is an N-type impurity, is ion-implanted into the cobalt silicide layer
6
with a dose of 1.0×10
16
ions/cm
2
and an ion implantation energy of 30 KeV.
Referring to
FIG. 1D
, after the arsenic is implanted, an annealing process is carried out to diffuse the arsenic ions implanted into the cobalt silicide layer
6
. As a result, an N-type impurity region
7
is formed on the substrate
1
, and arsenic ions are doped on the gate electrode
4
. The annealing process is performed at a temperature between 800° C. and 1000° C. to form a PN junction between the substrate
1
and the impurity region
7
.
FIG. 2
shows an analysis of an arsenic concentration distribution at the PN junction formed in the substrate
1
by using a secondary ion mass spectrometry (SIMS). As shown in
FIG. 2
, the higher the annealing temperature, the more the arsenic concentration is reduced.
According to the related method for fabricating the semiconductor device, the dopant is ion-implanted into the cobalt silicide layer. However, a considerable amount of the dopant escapes during the annealing process. Consequently, the PN junction is deteriorated, or a dopant shortage phenomenon occurs in the polysilicon gate electrode.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a semiconductor device which can improve a PN junction property. The preferred embodiments provide the benefit of preventing a dopant implanted into a cobalt silicide layer from escaping during an annealing process.
The object of the invention can be achieved in a whole or in part by a method for fabricating a semiconductor device including: forming a silicide layer at a predetermined portion of a semiconductor substrate; implanting first impurity ions into the silicide layer; implanting second impurity ions into the silicide layer; and annealing the silicide layer to diffuse the first and second impurity ions from the silicide layer to the substrate.
The object of the invention can also be achieved in a whole or in part by a method for fabricating a semiconductor device including: forming a gate insulation film at a predetermined portion over a semiconductor substrate; forming a gate electrode over the gate insulation film; forming sidewall spacers at first and second side walls of the gate electrode and the gate insulation film; forming a silicide layer over the semiconductor substrate adjacent to the sidewall spacers; implanting first impurity ions into the silicide layer; implanting second impurity ions into the silicide layer; and annealing the silicide layer to diffuse the first and second impurity ions from the silicide layer to the substrate.
The first and second implantation processes are performed by implanting one of arsenic (AS), phosphorous (P), boron fluoride (BF
2
), boron (B), silicon (Si) and argon (Ar) into the silicide layer. However, a dose of the impurity ions implanted into the silicide layer during the second implantation process is set lower than a dose of the impurity ions implanted during the first implantation process by a ratio of about 1/100 to 1/1000.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly poin
Park Ji Soo
Son Dong Kyun
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Rocchegiani Renzo N.
Smith Matthew
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