Method for fabricating semiconductor device

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S629000

Reexamination Certificate

active

08053341

ABSTRACT:
A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

REFERENCES:
patent: 7923766 (2011-04-01), Saito
patent: 7928504 (2011-04-01), Choi
patent: 2007/0267676 (2007-11-01), Kim et al.
patent: 2008/0003700 (2008-01-01), Wang et al.
patent: 2008/0284029 (2008-11-01), Kim et al.
patent: 2009/0057728 (2009-03-01), Boyle
patent: 2010/0200948 (2010-08-01), Kim
patent: 1020080030385 (2008-04-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on May 12, 2011.

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