Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2009-11-12
2010-10-26
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S584000, C438S586000, C438S614000, C438S622000, C438S672000, C257SE21290, C257SE21577, C257SE21582
Reexamination Certificate
active
07820537
ABSTRACT:
A method for fabricating a semiconductor device includes forming a polysilicon layer, a barrier metal layer, and a conductive layer over a substrate, forming gate hard masks over the conductive layer, etching the conductive layer and the barrier metal layer using the gate hard masks to form barrier metal electrodes and metal gate electrodes having a line width smaller than that of the gate hard masks, etching the polysilicon layer to form gate patterns, each gate pattern including a stack structure of a polysilicon electrode, the barrier metal electrode, the metal gate electrode, and the gate hard mask, forming a gate spacer over the surface profile of the substrate structure, forming an insulation layer over the gate spacer, etching the insulation layer to form a contact hole between the gate patterns and burying a conductive material over the contact hole to form a landing plug contact.
REFERENCES:
patent: 2004/0063286 (2004-04-01), Kim et al.
patent: 2006/0234447 (2006-10-01), Choi et al.
patent: 2008/0164511 (2008-07-01), Kim
patent: 2008/0169496 (2008-07-01), Keller et al.
Ahmadi Mohsen
Garber Charles D
Hynix / Semiconductor Inc.
IP & T Group LLP
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