Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-12-08
2009-08-04
Picardat, Kevin M (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S638000, C438S687000
Reexamination Certificate
active
07569479
ABSTRACT:
A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor substrate; forming a seed layer on the contact hole through electroless plating process; and forming a metal interconnection in the contact hole on the seed layer.
REFERENCES:
patent: 6197688 (2001-03-01), Simpson
patent: 6297154 (2001-10-01), Gross et al.
patent: 6316359 (2001-11-01), Simpson
patent: 6380083 (2002-04-01), Gross
patent: 6727176 (2004-04-01), Ngo et al.
patent: 2003/0216057 (2003-11-01), Hussein et al.
patent: 2005/0230263 (2005-10-01), Dubin
patent: 2007/0283886 (2007-12-01), Chung et al.
patent: 1226080 (1999-08-01), None
patent: 9-283557 (1997-10-01), None
patent: 10-0635685 (1999-12-01), None
patent: 2000-0017528 (2000-03-01), None
Michael Edith Gros and Christope Rink: Method for Constituting a Semiconductor Device Having a Copper Connection Portion: Mar. 25, 2000: Korean Patent Abstracts; Korean Intellectual Property Office, Republic of Korea.
The Semiconductor Device and Manufacturing Method [Semiconductor Equipment and Fabrication Method Thereof]; Korean Patent Registration No. 10-0635685: Published on Dec. 27, 1999: Korean Patent Abstracts; Korean Intellectual Property Office, Republic of Korea.
Office Action, Korean Patent Application No. 10-2005-0120587; 2 Pgs.; Dated Nov. 15, 2006: Korean Intellectual Property Office, Republic of Korea.
Cindy Reidsema Simpson; “Interconnect Structure in Semiconductor Device and Method of Formation”; esp@cenet; Abstract of US 6,197,688, corresponding to Chinese Patent No. CN1226080; Aug. 18, 1999; esp@cenet Database—Worldwide.
Hidenori Hayashida and Shigeaki Ueda; “Method of Electrical Connection of Electric Element Chip to Interconnection Circuit”; Patent Abstracts of Japan; Publication No. 09-283557; Publication Date: Oct. 31, 1997; Japan Patent Office, Japan.
Chinese Office Action issued May 23, 2008 and English Translation; Chinese Patent Application No. 200610164285.8; The State Intellectual Property Office of P.R.C., People's Republic of China.
Brow William E.
Dongbu Electronics Co. Ltd.
Fortney Andrew D.
Picardat Kevin M
The Law Offices of Andrew D. Fortney
LandOfFree
Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4055000