Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-30
2004-10-05
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S361000, C257S412000, C257S774000, C438S618000
Reexamination Certificate
active
06800907
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, a method for fabricating a semiconductor device improved on a confidence level in a hot carrier and a refresh characteristic.
DESCRIPTION OF RELATED ARTS
In general, a gate electrode is an electrode for selecting a metal oxide semiconductor (MOS) transistor and formed with a polysilicon layer doped mainly with impurities. Particularly, the gate electrode has a stacked structure of either a polysilicon layer doped with impurities and a tungsten silicide WSi
2
layer or a doped polysilicon and a titanium silicide TiSi
2
layer in order to reduce resistivity of the gate electrode.
However, in case of forming the gate electrode in the stacked structure of the doped polysilicon and the metal silicide layer, there is a problem for a highly integrated semiconductor device to obtain a lower resistance of the micro-gate electrode although the above-stacked structure is usefully applicable for a lowly integrated semiconductor device.
In other words, the tungsten silicide layer has the resistivity with a value of approximately 100&mgr;&OHgr;-cm. In a dynamic random access memory (hereinafter referred as to DRAM) device of which capacitance is in about 1 giga bites, resistance of the gate electrode should be decreased in more extents in order to develop a device operating with a high speed in a micro-line width.
Therefore, in case of a next generation semiconductor device to which a technology of a micro-circuit line width less than 0.13 &mgr;m is applied, the resistivity is approximately 10&mgr;&OHgr;-cm, and a single metal such as tungsten W, titanium Ti or molybdenum Mo is stacked on top of the polysilicon layer as to be used as a gate electrode. The reason for using the single metal for the polysilicon layer is because it has a higher conductivity than the tungsten silicide layer or titanium silicide layer.
FIGS. 1A and 1B
are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with a prior art.
With reference to
FIG. 1A
, a gate oxide layer
12
is formed on a substrate
11
, and then, a polysilicon layer
13
, a tungsten layer
14
and a hard mask
15
are sequentially deposited thereon.
Subsequently, a mask (not shown) for forming a gate electrode is formed on the hard mask
15
, which is, in turn, etched through the use of the mask. After the etching, the mask is removed. Then, the etched hard mask
15
etches the tungsten layer
14
and the polysilicon layer
13
so as to a gate electrode stacked in an order of the polysilicon layer
13
and the tungsten layer
14
.
Next, in the etching process for forming the gate electrode, damages provoked at a surface of the gate electrode
12
and remnants from the etching process are removed. In order to recover a confidence level of the gate oxide layer
12
, an oxide layer
13
A is formed on lateral sides of the polysilicon layer
13
through a re-oxidation process that re-oxidate selectively the polysilicon layer
13
.
Herein, proceeding of the re-oxidation process can prevent electric fields from concentrating at corners of the gate electrode.
Afterwards, a lowly concentrated impurity area
16
is formed on the substrate
11
through an ion implantation by using the gate electrode as a mask. In case of a typical n-metal oxide semiconductor field effect transistor (nMOSFET), the lowly concentrated impurity area
16
is called as a lightly doped drain (LDD) area. Then, an insulting layer
17
to be used for a spacer
18
(hereinafter referred as to spacer insulating layer) is deposited on an entire surface including the gate electrode.
As shown in
FIG. 1B
, the spacer insulating layer
17
is proceeded with an etchback process so that a spacer
18
contacting to lateral sides of the gate electrode is formed. At this time, the gate oxide layer
12
exposed on a surface of the substrate
11
during the formation of the spacer
18
is simultaneously etched as well.
Subsequently, high concentrations of impurities are ion implanted by using the gate electrode and the spacer
18
as a mask so to form a highly concentrated impurity area
19
connected electrically to the lowly concentrated impurity area
16
. Generally, the highly concentrated impurity area is called as source/drain area.
In the prior art as described above, the re-oxidation process is operated at a temperature greater than about 800° C. by proceeding a thermal oxidation process. Hence, the polysilicon layer
13
is selectively oxidated to prevent lateral sides of the tungsten layer
14
from being oxidated.
If the tungsten layer
14
is oxidated, a shape of the gate electrode is deteriorated, and thus, an effective line width of the tungsten layer
14
becomes significantly narrowed. As a result of this narrowed line width, it is difficult to obtain conductivity of the gate electrode.
However, the tungsten layer
14
, in accordance with the prior art, is easily oxidated at a temperature above about 400° C. An oxide provided through a low pressure chemical vapor deposition (hereinafter referred as to LPCVD) technique cannot be used for the spacer insulating layer
17
because a conditional temperature for the LPCVD technique is approximately 600° C.
For instance, in case of a high temperature oxide (HTO) layer provided through the LPCVD, a temperature for the deposition is greater than about 750° C. and N
2
O gas employed during the deposition is used to oxidate the tungsten layer
14
.
Also, in case of a low pressure tetra ethyl ortho silicate (LPTEOS) provided through the LPCVD technique, a layer is deposited through a heat decomposition of the TEOS at a temperature higher than about 600° C. However, oxygen released by the heat decomposition of the TEOS oxidates the tungsten layer
14
.
Therefore, when fabricating a semiconductor device that employs a metal such as tungsten as a gate electrode, a nitride layer provided through the LPCVD technique is used as a spacer so that the metal included in the gate electrode is suppressed from the oxidation.
However, in case of depositing the nitride immediately after the etching process for forming the gate electrode, there are disadvantages in that a lifetime of a hot carrier is decreased due to a stress concentrated at bottom corners of the gate electrode and characteristics of a device, e.g., gate induced drain leakage and refresh are degraded.
Consequently, it is recently attempted to adapt plasma enhanced tetra ethyl ortho silicate (PETEOS) as a spacer wherein a low thermal deposition is possible. However, the PETEOS is limited to be used for the spacer due to a lowered density of the PETEOS.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device capable of preventing an oxidation of a metal included in a gate electrode and suppressing a stress concentrated at bottom corners of the gate electrode. It is another object of the present invention to provide a semiconductor device improved on a quality of a gate oxide layer.
In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming a gate oxide layer on a substrate; forming a gate electrode including at least one metal layer on the gate oxide layer; forming an oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of the metal layer; and etching selectively the densified oxide layer so as to form an oxide spacer on the lateral sides of the gate electrode.
In accordance with another aspect of the present invention, there is also provided a method for fabricating a semiconductor device, comprising the steps of: forming a gate oxide layer on a substrate; forming a gate electrode by stacking a silicon based conductive layer and a metal layer on the gate oxide layer; forming an oxide layer on the substrate including the gate electrode at a temperature lower than oxidation temperature of th
Kim Jae-Ok
Kim Woo-Jin
Oh Jong-Hyuk
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Niebling John F.
Pompey Ron
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