Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-06-22
2000-11-21
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438533, 438682, H01L 213205, H01L 2144
Patent
active
061502480
ABSTRACT:
A method for fabricating a semiconductor device including a silicon region and a cobalt silicide film, the cobalt silicide film being in contact with at least a part of the silicon region. The method includes the steps of: doping at least part of the silicon region with boron by setting a doping level of boron in the part at 1.times.10.sup.15 cm.sup.-3 or more; depositing a cobalt film over a surface of the silicon region; conducting a first heat treatment for producing a silicidation reaction in a contact region between the cobalt film and the silicon region and thereby forming the cobalt silicide film; selectively removing unreacted portions of the cobalt film that have not been turned into silicide; and conducting a second heat treatment at a temperature higher than a temperature set for the first heat treatment step, thereby inducing a phase transition in the cobalt silicide film. The first heat treatment step is performed within a reducing ambient gas, and the temperature set for the first heat treatment step is in the range from about 400.degree. C. to about 600.degree. C., both inclusive.
REFERENCES:
patent: 5834368 (1998-11-01), Kawaguchi et al.
La Via., et al., "Electrical Characterization of Ultra-Shallow Junctions Formed by Diffusion from a CoSi2 Diffusion Source", Proc. of Mat. Res. Soc. Symp., vol. 427, pp. 493-498.
A.C. Berti, et al., "A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology", Proc. of VMIC Conference, pp. 267-273, Jun. 9-10, 1992.
J.A. Kittl, "Salicides for 0.10 um Gate Lengths: A Comparative Study of One-Step RTP Ti with Mo Doping, Ti with Preamorphization and Co Processes", Symposium on VLSI Technology Digest of Technical Papers, pp. 103-104, 1997.
S. Ogawa et al., "Epitaxial CoSi.sub.2 Layer Formation Technology on (100) Si and Its Application for Reduced Leakage, Ultra Shallow p.sup.+
Junction", Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, Makuhari, pp. 195-197, 1993 no month.
Berti et al, VMCI Conference, pp. 267-273, Jun. 1992.
Ogawa Shin-ichi
Sekiguchi Mitsuru
Sugiyama Tatsuo
Tsutsumi Kikuko
Ghyka Alexander G.
Matsushita Electronics Corporation
Niebling John F.
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