Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure
Reexamination Certificate
1999-10-29
2002-08-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Mesa structure
C257S622000, C257S048000, C257S769000
Reexamination Certificate
active
06437423
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and specifically to a method for fabricating semiconductor components with high aspect ratio features.
BACKGROUND OF THE INVENTION
Semiconductor components such as dice, and interconnects for electrically engaging dice, can include high aspect ratio features. A “high aspect ratio feature” means that a height, or depth, of the feature is several times greater than a width, or diameter, of the feature. For example, features having aspect ratios (e.g., height/width) of about 5 or more, are sometimes considered high aspect ratio features.
One example of a semiconductor component that includes high aspect ratio features is the interconnect described in U.S. Pat. Nos. 5,483,741 and 5,686,317 to Akram et al. This interconnect includes contact members adapted to electrically engage corresponding contact locations on a semiconductor die for testing. The contact members on the interconnect include projections etched on a silicon substrate. A representative height of the projections, measured from the surface of the substrate to the tips of the projections, can be between about 3 to 10 mils. A representative width of each side of the projections can be from 0.5 to 5 mils.
During fabrication of the interconnect, the projections must be covered with an electrically conductive layer. One method for forming the conductive layer includes a lithographic process, in which a metal is blanket deposited on the substrate, then etched using a photopatterned layer of resist. Typically, the resist is applied using a spin coater, which is adapted to apply a quantity of resist as the substrate is spun to distribute the resist.
This type of high aspect ratio feature is difficult cover with metal using conventional lithographic processes. In particular problems can occur because the resist tends to slide off the sidewalls and tips of the projections, and to pool on the surface of the substrate. This phenomena is sometimes referred to as poor step coverage. A thickness of the resist layer can also be uneven due to the uneven topography of the substrate. The poor step coverage, and unevenness of the resist layer, can produce defects during photopatterning of the resist to form an etch mask. The defects in the etch mask can produce defects in the subsequently formed conductive layer. In particular, the metal on contact projections not protected by resist can be etched away, so that portions of the projections are not covered with metal.
Components other than interconnects, such as semiconductor dice can also include high aspect ratio features that must subsequently be covered with a photopatterned metal layer. For example, U.S. Pat. No. 5,354,705 to Matthews et al. discloses a method for fabricating semiconductor container structures having a high aspect ratio. The container structures function to provide an increased surface area for storage capacitors. When it is necessary to apply photoresist to these non-planar topographies, conventional resist deposition and photopatterning processes can provide poor results. Specifically, the photoresist may not form with a uniform thickness over the non-planar features, and may not cover the tips and sidewalls of the features. When a metal layer covering the container structures is subsequently patterned, defects can occur.
The present invention is directed to an improved method for fabricating semiconductor structures having high aspect ratio features.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method for fabricating semiconductor structures having high aspect ratio features is provided. In an illustrative embodiment the method is used in the fabrication of an interconnect adapted to test semiconductor components, such as dice, wafers and chip scale packages. The interconnect includes a substrate with integrally formed contact members adapted to electrically engage contacts (e.g., bond pads) on the semiconductor components.
The method, simply stated, comprises forming the contact members with two conductive layers, which are patterned using two separate layers of thick film resist. A suitable thick film resist is a negative tone resist comprising an epoxy resin, an organic solvent, and a photo initiator. This resist can be deposited with a thickness greater than the height of features which form the contact members.
To perform the method, the substrate of the interconnect is provided with patterns of projections formed thereon. The locations of the projections match the locations of contacts on a semiconductor component that can be tested using the interconnect. Initially, a first conductive layer is blanket deposited on the projections and substrate. Preferably, the first conductive layer comprises a metal silicide. Next, a first resist mask, which has a thickness greater than a height of the projections, is used to protect the projections while the first conductive layer is etched. Following etching of the first conductive layer, only the projections remain covered by the first conductive layer. The first resist mask is then removed, and a second conductive layer is deposited on the covered projections and substrate. A second resist mask having a thickness less than a height of the projections, is then used to etch the second conductive layer from the tips of the projections. During this etch step, portions of the second conductive layer on the substrate are also etched to form conductive traces. Alternately, the conductive traces can be formed separately from the second conductive layer using a separate metallization process.
The resultant contact members include the projections having tip portions covered by the first conductive layer, but with sidewalls covered by stacks comprising both conductive layers. The second conductive layer can also forms the conductive traces on the substrate to provide electrical paths to the contact members.
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Clark Sheila V.
Gratton Stephen A.
Micro)n Technology, Inc.
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