Method for fabricating reverse-staggered thin film transistor

Details Method for fabricating reverse-staggered thin film transistor Method for fabricating reverse-staggered thin film transistor

2006-12-12

2010-02-16

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257SE21133

Reexamination Certificate

active

07662681

ABSTRACT:
Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.

REFERENCES:
patent: 2004/0241920 (2004-12-01), Hsiao et al.
patent: 2005/0170643 (2005-08-01), Fujii et al.

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